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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2003-2004 Jakub Jermar |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| Line 24... | Line 24... | ||
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32boot |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | */ |
33 | */ |
| - | 34 | ||
| 34 | #include "mm.h" |
35 | #include "mm.h" |
| 35 | 36 | ||
| - | 37 | /** Initializes section page table entry. |
|
| - | 38 | * |
|
| 36 | /** Set page table entry to point no frame, be read/write by kernel, |
39 | * Will be readable/writable by kernel with no access from user mode. |
| 37 | * no access by user, become to domain 0, no cache or buffer |
40 | * Will belong to domain 0. No cache or buffering is enabled. |
| - | 41 | * |
|
| 38 | * \param pte page table entry to set |
42 | * \param pte page table entry to set |
| 39 | * \param frame frame number of first frame 1MB section |
43 | * \param frame first frame in the section (frame number) |
| 40 | * Note: If frame not aligned it's used first lower 1MB aligned frame |
44 | * \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. |
| 41 | */ |
45 | */ |
| 42 | static void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){ |
46 | static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){ |
| 43 | pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
47 | pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
| 44 | pte->bufferable = 0; // disable |
48 | pte->bufferable = 0; // disable |
| 45 | pte->cacheable = 0; |
49 | pte->cacheable = 0; |
| 46 | pte->machine_depend = 0; |
50 | pte->machine_depend = 0; |
| 47 | pte->domain = 0; |
51 | pte->domain = 0; |
| Line 52... | Line 56... | ||
| 52 | }; |
56 | }; |
| 53 | 57 | ||
| 54 | 58 | ||
| 55 | void mm_kernel_mapping(void) { |
59 | void mm_kernel_mapping(void) { |
| 56 | int i; |
60 | int i; |
| - | 61 | ||
| - | 62 | const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
|
| 57 | // Create 1:1 mapping |
63 | // create 1:1 mapping (in lower 2GB) |
| 58 | for( i=0; i < PTL0_ENTRIES_ARCH; i++) { |
64 | for(i = 0; i < first_kernel_section; i++) { |
| 59 | init_pte_level0_section_entry(&page_table[i], i * FRAMES_PER_SECTION); |
65 | init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION); |
| 60 | } |
66 | } |
| 61 | 67 | ||
| 62 | // Create kernel mapping |
- | |
| 63 | const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
68 | // create kernel mapping (in upper 2GB), physical addresses starting from 0 |
| 64 | for( i = offset; i < PTL0_ENTRIES_ARCH; i++) { |
69 | for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) { |
| 65 | init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION); |
70 | init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION); |
| 66 | } |
71 | } |
| 67 | 72 | ||
| 68 | SET_PTL0_ADDRESS_ARCH( page_table); |
73 | set_ptl0_address(page_table); |
| 69 | 74 | ||
| 70 | // Enable paging |
75 | // enable paging |
| 71 | asm volatile ( |
76 | asm volatile ( |
| 72 | "ldr r0, =0x55555555 \n" |
77 | "ldr r0, =0x55555555 \n" |
| 73 | "mcr p15, 0, r0, c3, c0, 0 \n" // Set domain acces rights to client <==> take rights from page tables |
78 | "mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables |
| 74 | "mrc p15, 0, r0, c1, c0, 0 \n" // Get current setting of system ... register 1 isn't only for memmory management |
79 | "mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system |
| 75 | "ldr r1, =0xFFFFFE8D \n" // Mask to disable aligment checks; system & rom bit disable |
80 | "ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled |
| 76 | "and r0, r0, r1 \n" |
81 | "and r0, r0, r1 \n" |
| 77 | "ldr r1, =0x00000001 \n" // Mask to enable paging |
82 | "ldr r1, =0x00000001 \n" // mask to enable paging |
| 78 | "orr r0, r0, r1 \n" |
83 | "orr r0, r0, r1 \n" |
| 79 | "mcr p15, 0, r0, c1, c0, 0 \n" // Store setting |
84 | "mcr p15, 0, r0, c1, c0, 0 \n" // store settings |
| 80 | : |
85 | : |
| 81 | : |
86 | : |
| 82 | : "r0", "r1" |
87 | : "r0", "r1" |
| 83 | ); |
88 | ); |
| 84 | }; |
89 | }; |
| 85 | 90 | ||
| 86 | /** @} |
91 | /** @} |
| 87 | */ |
92 | */ |