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Line 49... Line 49...
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     */
 49 
     */
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 50 
 
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    cpu_priority_high();
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    cpu_priority_high();
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    cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
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    cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
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                        cp0_status_um_bit));
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                        cp0_status_um_bit));
- 
 
 54 
 
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    /* Save pstate so that the threads can access it */
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    /* Save pstate so that the threads can access it */
- 
 
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    /* If THREAD->pstate is set, this is nested exception,
- 
 
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     * do not rewrite it
- 
 
 58 
     */
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    if (THREAD)
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    if (THREAD && !THREAD->pstate)
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        THREAD->pstate = pstate;
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        THREAD->pstate = pstate;
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    /* decode exception number and process the exception */
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    /* decode exception number and process the exception */
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    switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
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    switch (excno = (cp0_cause_read() >> 2) & 0x1f) {
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        case EXC_Int:
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        case EXC_Int:
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            break;
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            break;
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        case EXC_TLBL:
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        case EXC_TLBL:
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        case EXC_TLBS:
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        case EXC_TLBS:
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            tlb_invalid(pstate);
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            tlb_invalid(pstate);
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            break;
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            break;
- 
 
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        case EXC_CpU:
- 
 
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#ifdef FPU_LAZY    
- 
 
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            scheduler_fpu_lazy_request();
- 
 
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#else
- 
 
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            panic("unhandled Coprocessor Unusable Exception\n");
- 
 
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#endif
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            break;
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        case EXC_Mod:
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        case EXC_Mod:
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            panic("unhandled TLB Modification Exception\n");
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            panic("unhandled TLB Modification Exception\n");
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            break;
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            break;
70 
        case EXC_AdEL:
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        case EXC_AdEL:
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            panic("unhandled Address Error Exception - load or instruction fetch\n");
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            panic("unhandled Address Error Exception - load or instruction fetch\n");
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            epc_shift = 4;
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            epc_shift = 4;
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            break;
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            break;
87 
        case EXC_RI:
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        case EXC_RI:
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            panic("unhandled Reserved Instruction Exception\n");
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            panic("unhandled Reserved Instruction Exception\n");
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            break;
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            break;
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        case EXC_CpU:
 - 
 
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#ifdef FPU_LAZY    
- 
 
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            scheduler_fpu_lazy_request();
 - 
 
93 
#else
 - 
 
94 
            panic("unhandled Coprocessor Unusable Exception\n");
 - 
 
95 
#endif
 - 
 
96 
            break;
 - 
 
97 
        case EXC_Ov:
 101 
        case EXC_Ov:
98 
            panic("unhandled Arithmetic Overflow Exception\n");
 102 
            panic("unhandled Arithmetic Overflow Exception\n");
99 
            break;
 103 
            break;
100 
        case EXC_Tr:
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        case EXC_Tr:
101 
            panic("unhandled Trap Exception\n");
 105 
            panic("unhandled Trap Exception\n");
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        default:
 119 
        default:
116 
            panic("unhandled exception %d\n", excno);
 120 
            panic("unhandled exception %d\n", excno);
117 
    }
 121 
    }
118 
   
 122 
   
119 
    pstate->epc += epc_shift;
 123 
    pstate->epc += epc_shift;
- 
 
 124 
    /* Set to NULL, so that we can still support nested
- 
 
 125 
     * exceptions
120 
    /* Probable not needed, but just for sure that nobody
 126 
     * TODO: We should probably set EXL bit before this command,
121 
     * will continue accessing it */
 127 
     * nesting. On the other hand, if some exception occurs between
- 
 
 128 
     * here and ERET, it won't set anything on the pstate anyway.
- 
 
 129 
     */
122 
    if (THREAD)
 130 
    if (THREAD)
123 
        THREAD->pstate = NULL;
 131 
        THREAD->pstate = NULL;
124 
}
 132 
}