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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_ie_enabled_bit   (1<<0)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_exl_exception_bit    (1<<1)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_im7_shift        15
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#define cp0_status_im7_shift        15
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/*
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/*
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 * Magic value for use in msim.
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 * Magic value for use in msim.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 * On AMD Duron 800Mhz, this roughly seems like one us.