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Line 112... Line 112...
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    l_apic_debug();
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    l_apic_debug();
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}
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}
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void apic_spurious(__u8 n, __u32 stack[])
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void apic_spurious(__u8 n, __u32 stack[])
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{
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{
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    printf("cpu%d: APIC spurious interrupt\n", the->cpu->id);
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    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
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}
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}
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int apic_poll_errors(void)
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int apic_poll_errors(void)
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{
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{
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    __u32 esr;
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    __u32 esr;
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    return !esr;
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    return !esr;
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}
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}
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/*
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/*
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 * Send all CPUs excluding the->cpu IPI vector.
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 * Send all CPUs excluding CPU IPI vector.
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 */
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 */
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int l_apic_broadcast_custom_ipi(__u8 vector)
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int l_apic_broadcast_custom_ipi(__u8 vector)
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{
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{
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    __u32 lo;
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    __u32 lo;
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    tmp = l_apic[SVR] & SVRClear;
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    tmp = l_apic[SVR] & SVRClear;
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    l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
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    l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
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    l_apic[TPR] &= TPRClear;
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    l_apic[TPR] &= TPRClear;
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    if (the->cpu->arch.family >= 6)
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    if (CPU->arch.family >= 6)
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        enable_l_apic_in_msr();
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        enable_l_apic_in_msr();
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    tmp = l_apic[ICRlo] & ICRloClear;
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    tmp = l_apic[ICRlo] & ICRloClear;
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    l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
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    l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
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void l_apic_debug(void)
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void l_apic_debug(void)
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{
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{
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#ifdef LAPIC_VERBOSE
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#ifdef LAPIC_VERBOSE
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    int i, lint;
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    int i, lint;
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    printf("LVT on cpu%d, LAPIC ID: %d\n", the->cpu->id, (l_apic[L_APIC_ID] >> 24)&0xf);
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    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, (l_apic[L_APIC_ID] >> 24)&0xf);
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    printf("LVT_Tm: ");
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    printf("LVT_Tm: ");
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    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
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    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
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    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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    printf("%B\n", l_apic[LVT_Err] & 0xff);
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    printf("%B\n", l_apic[LVT_Err] & 0xff);
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    /*
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    /*
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     * This register is supported only on P6 and higher.
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     * This register is supported only on P6 and higher.
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     */
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     */
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    if (the->cpu->family > 5) {
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    if (CPU->family > 5) {
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        printf("LVT_PCINT: ");
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        printf("LVT_PCINT: ");
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        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
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        switch ((l_apic[LVT_PCINT] >> 8)&7) {
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        switch ((l_apic[LVT_PCINT] >> 8)&7) {
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            case 0: printf("fixed"); break;
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            case 0: printf("fixed"); break;