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| Rev 1890 | Rev 1891 | ||
|---|---|---|---|
| Line 38... | Line 38... | ||
| 38 | #include <genarch/mm/asid_fifo.h> |
38 | #include <genarch/mm/asid_fifo.h> |
| 39 | #include <debug.h> |
39 | #include <debug.h> |
| 40 | 40 | ||
| 41 | #ifdef CONFIG_TSB |
41 | #ifdef CONFIG_TSB |
| 42 | #include <arch/mm/tsb.h> |
42 | #include <arch/mm/tsb.h> |
| - | 43 | #include <arch/memstr.h> |
|
| - | 44 | #include <synch/mutex.h> |
|
| - | 45 | #include <arch/asm.h> |
|
| - | 46 | #include <mm/frame.h> |
|
| - | 47 | #include <bitops.h> |
|
| - | 48 | #include <macros.h> |
|
| 43 | #endif |
49 | #endif |
| 44 | 50 | ||
| 45 | /** Architecture dependent address space init. */ |
51 | /** Architecture dependent address space init. */ |
| 46 | void as_arch_init(void) |
52 | void as_arch_init(void) |
| 47 | { |
53 | { |
| 48 | as_operations = &as_ht_operations; |
54 | as_operations = &as_ht_operations; |
| 49 | asid_fifo_init(); |
55 | asid_fifo_init(); |
| 50 | } |
56 | } |
| 51 | 57 | ||
| - | 58 | int as_constructor_arch(as_t *as, int flags) |
|
| - | 59 | { |
|
| - | 60 | #ifdef CONFIG_TSB |
|
| - | 61 | int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH); |
|
| - | 62 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags); |
|
| - | 63 | ||
| - | 64 | if (!tsb) |
|
| - | 65 | return -1; |
|
| - | 66 | ||
| - | 67 | as->arch.itsb = (tsb_entry_t *) tsb; |
|
| - | 68 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * sizeof(tsb_entry_t)); |
|
| - | 69 | #endif |
|
| - | 70 | return 0; |
|
| - | 71 | } |
|
| - | 72 | ||
| - | 73 | int as_destructor_arch(as_t *as) |
|
| - | 74 | { |
|
| - | 75 | #ifdef CONFIG_TSB |
|
| - | 76 | count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH; |
|
| - | 77 | frame_free((uintptr_t) as->arch.itsb); |
|
| - | 78 | return cnt; |
|
| - | 79 | #else |
|
| - | 80 | return 0; |
|
| - | 81 | #endif |
|
| - | 82 | } |
|
| - | 83 | ||
| - | 84 | int as_create_arch(as_t *as, int flags) |
|
| - | 85 | { |
|
| - | 86 | #ifdef CONFIG_TSB |
|
| - | 87 | ipl_t ipl; |
|
| - | 88 | ||
| - | 89 | memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0); |
|
| - | 90 | ipl = interrupts_disable(); |
|
| - | 91 | mutex_lock_active(&as->lock); /* completely unnecessary, but polite */ |
|
| - | 92 | tsb_invalidate(as, 0, (count_t) -1); |
|
| - | 93 | mutex_unlock(&as->lock); |
|
| - | 94 | interrupts_restore(ipl); |
|
| - | 95 | #endif |
|
| - | 96 | return 0; |
|
| - | 97 | } |
|
| - | 98 | ||
| 52 | /** Perform sparc64-specific tasks when an address space becomes active on the processor. |
99 | /** Perform sparc64-specific tasks when an address space becomes active on the processor. |
| 53 | * |
100 | * |
| 54 | * Install ASID and map TSBs. |
101 | * Install ASID and map TSBs. |
| 55 | * |
102 | * |
| 56 | * @param as Address space. |
103 | * @param as Address space. |
| Line 76... | Line 123... | ||
| 76 | ctx.v = 0; |
123 | ctx.v = 0; |
| 77 | ctx.context = as->asid; |
124 | ctx.context = as->asid; |
| 78 | mmu_secondary_context_write(ctx.v); |
125 | mmu_secondary_context_write(ctx.v); |
| 79 | 126 | ||
| 80 | #ifdef CONFIG_TSB |
127 | #ifdef CONFIG_TSB |
| 81 | if (as != AS_KERNEL) { |
- | |
| 82 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
128 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
| 83 | 129 | ||
| 84 | ASSERT(as->arch.itsb && as->arch.dtsb); |
130 | ASSERT(as->arch.itsb && as->arch.dtsb); |
| 85 | 131 | ||
| 86 | uintptr_t tsb = as->arch.itsb; |
132 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
| 87 | 133 | ||
| 88 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
134 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
| 89 | /* |
135 | /* |
| 90 | * TSBs were allocated from memory not covered |
136 | * TSBs were allocated from memory not covered |
| 91 | * by the locked 4M kernel DTLB entry. We need |
137 | * by the locked 4M kernel DTLB entry. We need |
| Line 102... | Line 148... | ||
| 102 | 148 | ||
| 103 | tsb_base.value = 0; |
149 | tsb_base.value = 0; |
| 104 | tsb_base.size = TSB_SIZE; |
150 | tsb_base.size = TSB_SIZE; |
| 105 | tsb_base.split = 0; |
151 | tsb_base.split = 0; |
| 106 | 152 | ||
| 107 | tsb_base.base = as->arch.itsb >> PAGE_WIDTH; |
153 | tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH; |
| 108 | itsb_base_write(tsb_base.value); |
154 | itsb_base_write(tsb_base.value); |
| 109 | tsb_base.base = as->arch.dtsb >> PAGE_WIDTH; |
155 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
| 110 | dtsb_base_write(tsb_base.value); |
156 | dtsb_base_write(tsb_base.value); |
| 111 | } |
- | |
| 112 | #endif |
157 | #endif |
| 113 | } |
158 | } |
| 114 | 159 | ||
| 115 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
160 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
| 116 | * |
161 | * |
| Line 127... | Line 172... | ||
| 127 | * because we only read members that are |
172 | * because we only read members that are |
| 128 | * currently read-only. |
173 | * currently read-only. |
| 129 | */ |
174 | */ |
| 130 | 175 | ||
| 131 | #ifdef CONFIG_TSB |
176 | #ifdef CONFIG_TSB |
| 132 | if (as != AS_KERNEL) { |
- | |
| 133 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
177 | uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
| 134 | 178 | ||
| 135 | ASSERT(as->arch.itsb && as->arch.dtsb); |
179 | ASSERT(as->arch.itsb && as->arch.dtsb); |
| 136 | 180 | ||
| 137 | uintptr_t tsb = as->arch.itsb; |
181 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
| 138 | 182 | ||
| 139 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
183 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
| 140 | /* |
184 | /* |
| 141 | * TSBs were allocated from memory not covered |
185 | * TSBs were allocated from memory not covered |
| 142 | * by the locked 4M kernel DTLB entry. We need |
186 | * by the locked 4M kernel DTLB entry. We need |
| 143 | * to demap the entry installed by as_install_arch(). |
187 | * to demap the entry installed by as_install_arch(). |
| 144 | */ |
188 | */ |
| 145 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
189 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); |
| 146 | } |
190 | } |
| 147 | - | ||
| 148 | } |
- | |
| 149 | #endif |
191 | #endif |
| 150 | } |
192 | } |
| 151 | 193 | ||
| 152 | /** @} |
194 | /** @} |
| 153 | */ |
195 | */ |