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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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void fpu_context_save(fpu_context_t *fctx)
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void fpu_context_save(fpu_context_t *fctx)
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{
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{
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    fprs_reg_t fprs;
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    fprs.value = fprs_read();
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    if (fprs.dl) {
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        /*
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         * The lower half of floating-point registers is dirty.
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         * Spill it to memory.
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         */
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        __asm__ volatile (
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    __asm__ volatile (
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            "std %%f0, %0\n"
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        "std %%f0, %0\n"
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            "std %%f2, %1\n"
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        "std %%f2, %1\n"
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            "std %%f4, %2\n"
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        "std %%f4, %2\n"
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            "std %%f6, %3\n"
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        "std %%f6, %3\n"
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            : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
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        : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
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              "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
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          "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
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              "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
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          "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
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              "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
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          "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
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        );
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    );
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        fprs.dl = false;
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    }
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    if (fprs.du) { 
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        /*
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    /*
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         * The upper half of floating-point registers is dirty.
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     * We need to split loading of the floating-point registers because
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         * Spill it to memory.
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     * GCC (4.1.1) can't handle more than 30 operands in one asm statement.
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         */
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     */
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        __asm__ volatile (
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    __asm__ volatile (
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            "std %%f32, %0\n"
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        "std %%f32, %0\n"
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            "std %%f34, %1\n"
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        "std %%f34, %1\n"
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            "std %%f36, %2\n"
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        "std %%f36, %2\n"
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            "std %%f38, %3\n"
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        "std %%f38, %3\n"
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            : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
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        : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
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              "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
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          "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
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              "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
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          "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
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              "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
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          "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
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        );
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    );
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        fprs.du = false;
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    }
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    fprs_write(fprs.value);
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    __asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
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    __asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr));
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}
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}
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void fpu_context_restore(fpu_context_t *fctx)
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void fpu_context_restore(fpu_context_t *fctx)
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{
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{
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    fprs_reg_t fprs;
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    fprs.value = fprs_read();
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    __asm__ volatile (
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    __asm__ volatile (
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        "ldd %0, %%f0\n"
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        "ldd %0, %%f0\n"
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        "ldd %1, %%f2\n"
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        "ldd %1, %%f2\n"
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        "ldd %2, %%f4\n"
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        "ldd %2, %%f4\n"
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        "ldd %3, %%f6\n"
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        "ldd %3, %%f6\n"
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          "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
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          "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
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          "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
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          "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
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          "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
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          "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
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    );
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    );
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    fprs.dl = fprs.du = false;
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    fprs_write(fprs.value);
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172 
   
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    __asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
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    __asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr));
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}
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}
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void fpu_enable(void)
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void fpu_enable(void)
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{
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{