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69 | #define RR13 13 |
69 | #define RR13 13 |
70 | #define RR14 14 |
70 | #define RR14 14 |
71 | #define RR15 15 |
71 | #define RR15 15 |
72 | 72 | ||
73 | /* Write Register 0 */ |
73 | /* Write Register 0 */ |
- | 74 | #define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */ |
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74 | #define WR0_ERR_RST (0x6<<3) |
75 | #define WR0_ERR_RST (0x6<<3) |
75 | 76 | ||
76 | /* Write Register 1 */ |
77 | /* Write Register 1 */ |
77 | #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
78 | #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
78 | #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
79 | #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |