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#include <arch/types.h>
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#include <arch/types.h>
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#include <arch/register.h>
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#include <arch/register.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#ifdef CONFIG_SMP
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#include <arch/mm/cache.h>
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#endif
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#define MANUF_FUJITSU       0x04
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#define MANUF_FUJITSU       0x04
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#define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
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#define MANUF_ULTRASPARC    0x17    /**< UltraSPARC I, UltraSPARC II */
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#define MANUF_SUN       0x3e
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#define MANUF_SUN       0x3e
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#define IMPL_ULTRASPARCI    0x10
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#define IMPL_ULTRASPARCI    0x10
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#define IMPL_ULTRASPARCIV_PLUS  0x19
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#define IMPL_ULTRASPARCIV_PLUS  0x19
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#define IMPL_SPARC64V       0x5
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#define IMPL_SPARC64V       0x5
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typedef struct {
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typedef struct {
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    uint32_t mid;           /**< Processor ID as read from UPA_CONFIG. */
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    uint32_t mid;           /**< Processor ID as read from
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                         UPA_CONFIG. */
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    ver_reg_t ver;
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    ver_reg_t ver;
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    uint32_t clock_frequency;   /**< Processor frequency in Hz. */
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    uint32_t clock_frequency;   /**< Processor frequency in Hz. */
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    uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
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    uint64_t next_tick_cmpr;    /**< Next clock interrupt should be
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                                     generated when the TICK register
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                         generated when the TICK register
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                                     matches this value. */
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                         matches this value. */
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#ifdef CONFIG_SMP
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    int dcache_active;
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    dcache_shootdown_msg_t dcache_messages[DCACHE_MSG_QUEUE_LEN];
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    count_t dcache_message_count;
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#endif
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} cpu_arch_t;
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} cpu_arch_t;
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#endif
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#endif
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/** @}
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/** @}