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| Rev 1902 | Rev 1903 | ||
|---|---|---|---|
| Line 94... | Line 94... | ||
| 94 | } |
94 | } |
| 95 | 95 | ||
| 96 | static inline long test_and_set(atomic_t *val) |
96 | static inline long test_and_set(atomic_t *val) |
| 97 | { |
97 | { |
| 98 | uint64_t v = 1; |
98 | uint64_t v = 1; |
| - | 99 | volatile uintptr_t x = (uint64_t) &val->count; |
|
| 99 | 100 | ||
| 100 | __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (v) : "r" (0)); |
101 | __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
| 101 | 102 | ||
| 102 | return v; |
103 | return v; |
| 103 | } |
104 | } |
| 104 | 105 | ||
| 105 | static inline void atomic_lock_arch(atomic_t *val) |
106 | static inline void atomic_lock_arch(atomic_t *val) |
| 106 | { |
107 | { |
| 107 | uint64_t tmp1 = 1; |
108 | uint64_t tmp1 = 1; |
| 108 | uint64_t tmp2; |
109 | uint64_t tmp2; |
| 109 | 110 | ||
| - | 111 | volatile uintptr_t x = (uint64_t) &val->count; |
|
| - | 112 | ||
| 110 | __asm__ volatile ( |
113 | __asm__ volatile ( |
| 111 | "0:\n" |
114 | "0:\n" |
| 112 | "casx %0, %3, %1\n" |
115 | "casx %0, %3, %1\n" |
| 113 | "brz %1, 2f\n" |
116 | "brz %1, 2f\n" |
| 114 | "nop\n" |
117 | "nop\n" |
| Line 117... | Line 120... | ||
| 117 | "brz %2, 0b\n" |
120 | "brz %2, 0b\n" |
| 118 | "nop\n" |
121 | "nop\n" |
| 119 | "ba 1b\n" |
122 | "ba 1b\n" |
| 120 | "nop\n" |
123 | "nop\n" |
| 121 | "2:\n" |
124 | "2:\n" |
| 122 | : "+m" (*val), "+r" (tmp1), "+r" (tmp2) : "r" (0) |
125 | : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0) |
| 123 | ); |
126 | ); |
| 124 | 127 | ||
| 125 | /* |
128 | /* |
| 126 | * Prevent critical section code from bleeding out this way up. |
129 | * Prevent critical section code from bleeding out this way up. |
| 127 | */ |
130 | */ |