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}
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}
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static inline long test_and_set(atomic_t *val)
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static inline long test_and_set(atomic_t *val)
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{
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{
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    uint64_t v = 1;
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    uint64_t v = 1;
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    volatile uintptr_t x = (uint64_t) &val->count;
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    __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*val), "+r" (v) : "r" (0));
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    __asm__ volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0));
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    return v;
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    return v;
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}
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}
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static inline void atomic_lock_arch(atomic_t *val)
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static inline void atomic_lock_arch(atomic_t *val)
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{
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{
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    uint64_t tmp1 = 1;
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    uint64_t tmp1 = 1;
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    uint64_t tmp2;
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    uint64_t tmp2;
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    volatile uintptr_t x = (uint64_t) &val->count;
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    __asm__ volatile (
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    __asm__ volatile (
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    "0:\n"
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    "0:\n"
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        "casx %0, %3, %1\n"
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        "casx %0, %3, %1\n"
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        "brz %1, 2f\n"
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        "brz %1, 2f\n"
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        "nop\n"
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        "nop\n"
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        "brz %2, 0b\n"
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        "brz %2, 0b\n"
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        "nop\n"
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        "nop\n"
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        "ba 1b\n"
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        "ba 1b\n"
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        "nop\n"
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        "nop\n"
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    "2:\n"
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    "2:\n"
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        : "+m" (*val), "+r" (tmp1), "+r" (tmp2) : "r" (0)
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        : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0)
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    );
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    );
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    /*
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    /*
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     * Prevent critical section code from bleeding out this way up.
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     * Prevent critical section code from bleeding out this way up.
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     */
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     */