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Rev 1888 | Rev 1936 | ||
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Line 37... | Line 37... | ||
37 | #include <arch/types.h> |
37 | #include <arch/types.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | #include <arch/cp0.h> |
39 | #include <arch/cp0.h> |
40 | #include <time/clock.h> |
40 | #include <time/clock.h> |
41 | #include <arch/drivers/arc.h> |
41 | #include <arch/drivers/arc.h> |
42 | - | ||
43 | #include <ipc/sysipc.h> |
42 | #include <ipc/sysipc.h> |
- | 43 | #include <ddi/device.h> |
|
- | 44 | #include <ddi/irq.h> |
|
- | 45 | ||
- | 46 | #define IRQ_COUNT 8 |
|
- | 47 | #define TIMER_IRQ 7 |
|
- | 48 | ||
- | 49 | function timer_fnc = NULL; |
|
- | 50 | static irq_t timer_irq; |
|
44 | 51 | ||
45 | /** Disable interrupts. |
52 | /** Disable interrupts. |
46 | * |
53 | * |
47 | * @return Old interrupt priority level. |
54 | * @return Old interrupt priority level. |
48 | */ |
55 | */ |
Line 89... | Line 96... | ||
89 | { |
96 | { |
90 | nextcount = cp0_compare_value + cp0_count_read(); |
97 | nextcount = cp0_compare_value + cp0_count_read(); |
91 | cp0_compare_write(nextcount); |
98 | cp0_compare_write(nextcount); |
92 | } |
99 | } |
93 | 100 | ||
- | 101 | static irq_ownership_t timer_claim(void) |
|
- | 102 | { |
|
- | 103 | return IRQ_ACCEPT; |
|
- | 104 | } |
|
- | 105 | ||
94 | static void timer_exception(int n, istate_t *istate) |
106 | static void timer_irq_handler(irq_t *irq, void *arg, ...) |
95 | { |
107 | { |
96 | unsigned long drift; |
108 | unsigned long drift; |
97 | 109 | ||
98 | drift = cp0_count_read() - nextcount; |
110 | drift = cp0_count_read() - nextcount; |
99 | while (drift > cp0_compare_value) { |
111 | while (drift > cp0_compare_value) { |
Line 101... | Line 113... | ||
101 | CPU->missed_clock_ticks++; |
113 | CPU->missed_clock_ticks++; |
102 | } |
114 | } |
103 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
115 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
104 | cp0_compare_write(nextcount); |
116 | cp0_compare_write(nextcount); |
105 | clock(); |
117 | clock(); |
106 | } |
- | |
107 | 118 | ||
108 | static void swint0(int n, istate_t *istate) |
- | |
109 | { |
- | |
110 | cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */ |
- | |
111 | ipc_irq_send_notif(0); |
119 | if (timer_fnc != NULL) |
112 | } |
- | |
113 | - | ||
114 | static void swint1(int n, istate_t *istate) |
- | |
115 | { |
- | |
116 | cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */ |
- | |
117 | ipc_irq_send_notif(1); |
120 | timer_fnc(); |
118 | } |
121 | } |
119 | 122 | ||
120 | /* Initialize basic tables for exception dispatching */ |
123 | /* Initialize basic tables for exception dispatching */ |
121 | void interrupt_init(void) |
124 | void interrupt_init(void) |
122 | { |
125 | { |
123 | int_register(TIMER_IRQ, "timer", timer_exception); |
- | |
124 | int_register(0, "swint0", swint0); |
- | |
125 | int_register(1, "swint1", swint1); |
126 | irq_init(IRQ_COUNT, IRQ_COUNT); |
126 | timer_start(); |
- | |
127 | } |
- | |
128 | 127 | ||
- | 128 | irq_initialize(&timer_irq); |
|
129 | static void ipc_int(int n, istate_t *istate) |
129 | timer_irq.devno = device_assign_devno(); |
130 | { |
- | |
- | 130 | timer_irq.inr = TIMER_IRQ; |
|
- | 131 | timer_irq.claim = timer_claim; |
|
131 | ipc_irq_send_notif(n-INT_OFFSET); |
132 | timer_irq.handler = timer_irq_handler; |
132 | } |
- | |
- | 133 | irq_register(&timer_irq); |
|
133 | 134 | ||
134 | /* Reregister irq to be IPC-ready */ |
- | |
135 | void irq_ipc_bind_arch(unative_t irq) |
- | |
136 | { |
- | |
137 | /* Do not allow to redefine timer */ |
- | |
138 | /* Swint0, Swint1 are already handled */ |
- | |
139 | if (irq == TIMER_IRQ || irq < 2) |
- | |
140 | return; |
135 | timer_start(); |
141 | int_register(irq, "ipc_int", ipc_int); |
136 | cp0_unmask_int(TIMER_IRQ); |
142 | } |
137 | } |
143 | 138 | ||
144 | /** @} |
139 | /** @} |
145 | */ |
140 | */ |