WebSVN – HelenOS – Diff – /trunk/kernel/arch/ia64/src/mm/tlb.c

     default:
-        ps=PAGE_WIDTH+18;
+        ps = PAGE_WIDTH + 18;
-        va&=~((1<<ps)-1);
+        va &= ~((1 << ps) - 1);
         break;
+    }
-    for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
+    for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps))
-        asm volatile (
-            "ptc.l %0,%1;;"
-            :
-            : "r" (va), "r" (ps<<2)
+        asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2));
-        );
-    }
     srlz_d();
     srlz_i();
     if (restore_rr) {
         rr_write(VA2VRN(va), rr.word);
 /** Insert data into data translation cache.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
  */
 void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
+{
     tc_mapping_insert(va, asid, entry, true);
+}
 /** Insert data into instruction translation cache.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
  */
 void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry)
+{
     tc_mapping_insert(va, asid, entry, false);
+}
 /** Insert data into instruction or data translation cache.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
- * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
+ * @param dtc       If true, insert into data translation cache, use
+ *          instruction translation cache otherwise.
  */
 void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc)
+{
     region_register rr;
     bool restore_rr = false;
         "(p6) itc.i %3;;\n"
         "(p7) itc.d %3;;\n"
-        "mov psr.l=r8;;\n"
+        "mov psr.l = r8;;\n"
         "srlz.d;;\n"
+        :
-        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
+        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+            "r" (entry.word[0]), "r" (dtc)
         : "p6", "p7", "r8"
     );
     if (restore_rr) {
         rr_write(VA2VRN(va), rr.word);
 /** Insert data into instruction translation register.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
- * @param tr Translation register.
+ * @param tr        Translation register.
  */
+void
-void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+{
     tr_mapping_insert(va, asid, entry, false, tr);
+}
 /** Insert data into data translation register.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
- * @param tr Translation register.
+ * @param tr        Translation register.
  */
+void
-void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
+{
     tr_mapping_insert(va, asid, entry, true, tr);
+}
 /** Insert data into instruction or data translation register.
+ *
- * @param va Virtual page address.
+ * @param va        Virtual page address.
- * @param asid Address space identifier.
+ * @param asid      Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param entry     The rest of TLB entry as required by TLB insertion
+ *          format.
- * @param dtr If true, insert into data translation register, use instruction translation register otherwise.
+ * @param dtr       If true, insert into data translation register, use
+ *          instruction translation register otherwise.
- * @param tr Translation register.
+ * @param tr        Translation register.
  */
+void
-void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
+tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
+    index_t tr)
+{
     region_register rr;
     bool restore_rr = false;
     rr.word = rr_read(VA2VRN(va));
-        "(p6) itr.i itr[%4]=%3;;\n"
+        "(p6) itr.i itr[%4] = %3;;\n"
-        "(p7) itr.d dtr[%4]=%3;;\n"
+        "(p7) itr.d dtr[%4] = %3;;\n"
-        "mov psr.l=r8;;\n"
+        "mov psr.l = r8;;\n"
         "srlz.d;;\n"
+        :
-        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
+        : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]),
+            "r" (entry.word[0]), "r" (tr), "r" (dtr)
         : "p6", "p7", "r8"
     );
     if (restore_rr) {
         rr_write(VA2VRN(va), rr.word);
 /** Insert data into DTLB.
+ *
- * @param page Virtual page address including VRN bits.
+ * @param page      Virtual page address including VRN bits.
- * @param frame Physical frame address.
+ * @param frame     Physical frame address.
- * @param dtr If true, insert into data translation register, use data translation cache otherwise.
+ * @param dtr       If true, insert into data translation register, use data
+ *          translation cache otherwise.
- * @param tr Translation register if dtr is true, ignored otherwise.
+ * @param tr        Translation register if dtr is true, ignored otherwise.
  */
+void
-void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr)
+dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
+    index_t tr)
+{
     tlb_entry_t entry;
     entry.word[0] = 0;
     entry.word[1] = 0;
          * Forward the page fault to address space page fault handler.
          */
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
             fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+                istate->cr_iip);
+        }
+    }
+}
 static int is_io_page_accessible(int page)
+{
+    if (TASK->arch.iomap)
-    if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page);
+        return bitmap_get(TASK->arch.iomap,page);
+    else
-    else return 0;
+        return 0;
+}
 #define IO_FRAME_BASE 0xFFFFC000000
+/**
-/** There is special handling of memmaped lagacy io, because
+ * There is special handling of memory mapped legacy io, because of 4KB sized
- * of 4KB sized access
- * only for userspace
+ * access for userspace.
+ *
- * @param va virtual address of page fault
+ * @param va        Virtual address of page fault.
- * @param istate Structure with saved interruption state.
+ * @param istate    Structure with saved interruption state.
+ *
- *
- * @return 1 on success, 0 on fail
+ * @return      One on success, zero on failure.
  */
 static int try_memmap_io_insertion(uintptr_t va, istate_t *istate)
+{
-    if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH)))
+    if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) {
-        if(TASK){
+        if (TASK) {
+            uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >>
+                USPACE_IO_PAGE_WIDTH;
-            uint64_t io_page=(va &  ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH);
-            if(is_io_page_accessible(io_page)){
+            if (is_io_page_accessible(io_page)) {
-                uint64_t page,frame;
+                uint64_t page, frame;
+                page = IO_OFFSET +
-                page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+                frame = IO_FRAME_BASE +
-                frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page;
+                    (1 << USPACE_IO_PAGE_WIDTH) * io_page;
                 tlb_entry_t entry;
                 entry.word[0] = 0;
                 entry.word[1] = 0;
                 entry.ps = USPACE_IO_PAGE_WIDTH;
                 dtc_mapping_insert(page, TASK->as->asid, entry);
                 return 1;
-            }else {
+            } else {
+                fault_if_from_uspace(istate,
-                fault_if_from_uspace(istate,"IO access fault at %p",va);
+                    "IO access fault at %p", va);
-                return 0;
+            }
+        }
+    }
-        } else
-            return 0;
-    else
-        return 0;
     return 0;
+}
 /** Data TLB fault handler for faults with VHPT turned off.
+ *
- * @param vector Interruption vector.
+ * @param vector    Interruption vector.
- * @param istate Structure with saved interruption state.
+ * @param istate    Structure with saved interruption state.
  */
          */
         dtc_pte_copy(t);
         page_table_unlock(AS, true);
     } else {
         page_table_unlock(AS, true);
-        if (try_memmap_io_insertion(va,istate)) return;
+        if (try_memmap_io_insertion(va, istate))
+            return;
         /*
-         * Forward the page fault to the address space page fault handler.
+         * Forward the page fault to the address space page fault
+         * handler.
          */
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
             fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
+                istate->cr_iip);
+        }
+    }
+}
 /** Data nested TLB fault handler.
         t->d = true;
         dtc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
             fault_if_from_uspace(istate,"Page fault at %p",va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
-            t->d = true;
-            dtc_pte_copy(t);
+                istate->cr_iip);
+        }
+    }
     page_table_unlock(AS, true);
+}
         t->a = true;
         itc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
+            fault_if_from_uspace(istate, "Page fault at %p", va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
-            t->a = true;
-            itc_pte_copy(t);
+                istate->cr_iip);
+        }
+    }
     page_table_unlock(AS, true);
+}
         t->a = true;
         dtc_pte_copy(t);
     } else {
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
-            fault_if_from_uspace(istate,"Page fault at %p",va);
+            fault_if_from_uspace(istate, "Page fault at %p", va);
-            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip);
+            panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid,
-            t->a = true;
-            itc_pte_copy(t);
+                istate->cr_iip);
+        }
+    }
     page_table_unlock(AS, true);
+}

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/ia64/src/mm/tlb.c – Rev 3763 → 3766