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| 35 | 35 | ||
| 36 | #include <fpu_context.h> |
36 | #include <fpu_context.h> |
| 37 | #include <arch/register.h> |
37 | #include <arch/register.h> |
| 38 | #include <print.h> |
38 | #include <print.h> |
| 39 | 39 | ||
| 40 | - | ||
| 41 | void fpu_context_save(fpu_context_t *fctx){ |
40 | void fpu_context_save(fpu_context_t *fctx) |
| 42 | 41 | { |
|
| 43 | asm volatile( |
42 | asm volatile ( |
| 44 | - | ||
| 45 | "stf.spill [%0]=f32,0x80\n" |
43 | "stf.spill [%0] = f32, 0x80\n" |
| 46 | "stf.spill [%1]=f33,0x80\n" |
44 | "stf.spill [%1] = f33, 0x80\n" |
| 47 | "stf.spill [%2]=f34,0x80\n" |
45 | "stf.spill [%2] = f34, 0x80\n" |
| 48 | "stf.spill [%3]=f35,0x80\n" |
46 | "stf.spill [%3] = f35, 0x80\n" |
| 49 | "stf.spill [%4]=f36,0x80\n" |
47 | "stf.spill [%4] = f36, 0x80\n" |
| Line 112... | Line 110... | ||
| 112 | "stf.spill [%4]=f92,0x80\n" |
110 | "stf.spill [%4] = f92, 0x80\n" |
| 113 | "stf.spill [%5]=f93,0x80\n" |
111 | "stf.spill [%5] = f93, 0x80\n" |
| 114 | "stf.spill [%6]=f94,0x80\n" |
112 | "stf.spill [%6] = f94, 0x80\n" |
| 115 | "stf.spill [%7]=f95,0x80\n;;" |
113 | "stf.spill [%7] = f95, 0x80\n;;" |
| 116 | 114 | ||
| 117 | - | ||
| 118 | "stf.spill [%0]=f96,0x80\n" |
115 | "stf.spill [%0] = f96, 0x80\n" |
| 119 | "stf.spill [%1]=f97,0x80\n" |
116 | "stf.spill [%1] = f97, 0x80\n" |
| 120 | "stf.spill [%2]=f98,0x80\n" |
117 | "stf.spill [%2] = f98, 0x80\n" |
| 121 | "stf.spill [%3]=f99,0x80\n" |
118 | "stf.spill [%3] = f99, 0x80\n" |
| 122 | "stf.spill [%4]=f100,0x80\n" |
119 | "stf.spill [%4] = f100, 0x80\n" |
| Line 149... | Line 146... | ||
| 149 | "stf.spill [%4]=f124,0x80\n" |
146 | "stf.spill [%4] = f124, 0x80\n" |
| 150 | "stf.spill [%5]=f125,0x80\n" |
147 | "stf.spill [%5] = f125, 0x80\n" |
| 151 | "stf.spill [%6]=f126,0x80\n" |
148 | "stf.spill [%6] = f126, 0x80\n" |
| 152 | "stf.spill [%7]=f127,0x80\n;;" |
149 | "stf.spill [%7] = f127, 0x80\n;;" |
| 153 | 150 | ||
| 154 | - | ||
| 155 | : |
151 | : |
| 156 | :"r" (&((fctx->fr)[0])),"r" (&((fctx->fr)[1])),"r" (&((fctx->fr)[2])),"r" (&((fctx->fr)[3])), |
152 | : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| 157 | "r" (&((fctx->fr)[4])),"r" (&((fctx->fr)[5])),"r" (&((fctx->fr)[6])),"r" (&((fctx->fr)[7])) |
153 | "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| 158 | ); |
154 | ); |
| 159 | 155 | ||
| 160 | } |
156 | } |
| 161 | 157 | ||
| 162 | - | ||
| 163 | void fpu_context_restore(fpu_context_t *fctx) |
158 | void fpu_context_restore(fpu_context_t *fctx) |
| 164 | { |
159 | { |
| 165 | - | ||
| 166 | asm volatile( |
160 | asm volatile ( |
| 167 | "ldf.fill f32=[%0],0x80\n" |
161 | "ldf.fill f32 = [%0], 0x80\n" |
| 168 | "ldf.fill f33=[%1],0x80\n" |
162 | "ldf.fill f33 = [%1], 0x80\n" |
| 169 | "ldf.fill f34=[%2],0x80\n" |
163 | "ldf.fill f34 = [%2], 0x80\n" |
| 170 | "ldf.fill f35=[%3],0x80\n" |
164 | "ldf.fill f35 = [%3], 0x80\n" |
| Line 234... | Line 228... | ||
| 234 | "ldf.fill f92=[%4],0x80\n" |
228 | "ldf.fill f92 = [%4], 0x80\n" |
| 235 | "ldf.fill f93=[%5],0x80\n" |
229 | "ldf.fill f93 = [%5], 0x80\n" |
| 236 | "ldf.fill f94=[%6],0x80\n" |
230 | "ldf.fill f94 = [%6], 0x80\n" |
| 237 | "ldf.fill f95=[%7],0x80\n;;" |
231 | "ldf.fill f95 = [%7], 0x80\n;;" |
| 238 | 232 | ||
| 239 | - | ||
| 240 | "ldf.fill f96=[%0],0x80\n" |
233 | "ldf.fill f96 = [%0], 0x80\n" |
| 241 | "ldf.fill f97=[%1],0x80\n" |
234 | "ldf.fill f97 = [%1], 0x80\n" |
| 242 | "ldf.fill f98=[%2],0x80\n" |
235 | "ldf.fill f98 = [%2], 0x80\n" |
| 243 | "ldf.fill f99=[%3],0x80\n" |
236 | "ldf.fill f99 = [%3], 0x80\n" |
| 244 | "ldf.fill f100=[%4],0x80\n" |
237 | "ldf.fill f100 = [%4], 0x80\n" |
| Line 271... | Line 264... | ||
| 271 | "ldf.fill f124=[%4],0x80\n" |
264 | "ldf.fill f124 = [%4], 0x80\n" |
| 272 | "ldf.fill f125=[%5],0x80\n" |
265 | "ldf.fill f125 = [%5], 0x80\n" |
| 273 | "ldf.fill f126=[%6],0x80\n" |
266 | "ldf.fill f126 = [%6], 0x80\n" |
| 274 | "ldf.fill f127=[%7],0x80\n;;" |
267 | "ldf.fill f127 = [%7], 0x80\n;;" |
| 275 | 268 | ||
| 276 | - | ||
| 277 | : |
269 | : |
| 278 | :"r" (&((fctx->fr)[0])),"r" (&((fctx->fr)[1])),"r" (&((fctx->fr)[2])),"r" (&((fctx->fr)[3])), |
270 | : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| 279 | "r" (&((fctx->fr)[4])),"r" (&((fctx->fr)[5])),"r" (&((fctx->fr)[6])),"r" (&((fctx->fr)[7])) |
271 | "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| 280 | ); |
272 | ); |
| 281 | } |
273 | } |
| 282 | 274 | ||
| 283 | void fpu_enable(void) |
275 | void fpu_enable(void) |
| 284 | { |
276 | { |
| 285 | uint64_t a = 0 ; |
277 | uint64_t a = 0 ; |
| - | 278 | ||
| 286 | asm volatile( |
279 | asm volatile ( |
| 287 | "rsm %0;;" |
280 | "rsm %0 ;;" |
| 288 | "srlz.i\n" |
281 | "srlz.i\n" |
| 289 | "srlz.d;;\n" |
282 | "srlz.d ;;\n" |
| 290 | : |
283 | : |
| 291 | :"i" (PSR_DFH_MASK) |
284 | : "i" (PSR_DFH_MASK) |
| 292 | ); |
285 | ); |
| - | 286 | ||
| 293 | asm volatile |
287 | asm volatile ( |
| 294 | ( |
- | |
| 295 | "mov %0=ar.fpsr;;\n" |
288 | "mov %0 = ar.fpsr ;;\n" |
| 296 | "or %0=%0,%1;;\n" |
289 | "or %0 = %0,%1 ;;\n" |
| 297 | "mov ar.fpsr=%0;;\n" |
290 | "mov ar.fpsr = %0 ;;\n" |
| 298 | : "+r" (a) |
291 | : "+r" (a) |
| 299 | : "r" (0x38) |
292 | : "r" (0x38) |
| 300 | ); |
293 | ); |
| 301 | - | ||
| 302 | } |
294 | } |
| 303 | 295 | ||
| 304 | void fpu_disable(void) |
296 | void fpu_disable(void) |
| 305 | { |
297 | { |
| 306 | - | ||
| 307 | uint64_t a = 0 ; |
298 | uint64_t a = 0 ; |
| - | 299 | ||
| 308 | asm volatile( |
300 | asm volatile ( |
| 309 | "ssm %0;;\n" |
301 | "ssm %0 ;;\n" |
| 310 | "srlz.i\n" |
302 | "srlz.i\n" |
| 311 | "srlz.d;;\n" |
303 | "srlz.d ;;\n" |
| 312 | : |
304 | : |
| 313 | :"i" (PSR_DFH_MASK) |
305 | : "i" (PSR_DFH_MASK) |
| 314 | ); |
306 | ); |
| - | 307 | ||
| 315 | asm volatile |
308 | asm volatile ( |
| 316 | ( |
- | |
| 317 | "mov %0=ar.fpsr;;\n" |
309 | "mov %0 = ar.fpsr ;;\n" |
| 318 | "or %0=%0,%1;;\n" |
310 | "or %0 = %0,%1 ;;\n" |
| 319 | "mov ar.fpsr=%0;;\n" |
311 | "mov ar.fpsr = %0 ;;\n" |
| 320 | : "+r" (a) |
312 | : "+r" (a) |
| 321 | : "r" (0x38) |
313 | : "r" (0x38) |
| 322 | ); |
314 | ); |
| 323 | - | ||
| 324 | } |
315 | } |
| 325 | 316 | ||
| 326 | void fpu_init(void) |
317 | void fpu_init(void) |
| 327 | { |
318 | { |
| 328 | uint64_t a = 0 ; |
319 | uint64_t a = 0 ; |
| - | 320 | ||
| 329 | asm volatile |
321 | asm volatile ( |
| 330 | ( |
- | |
| 331 | "mov %0=ar.fpsr;;\n" |
322 | "mov %0 = ar.fpsr ;;\n" |
| 332 | "or %0=%0,%1;;\n" |
323 | "or %0 = %0,%1 ;;\n" |
| 333 | "mov ar.fpsr=%0;;\n" |
324 | "mov ar.fpsr = %0 ;;\n" |
| 334 | : "+r" (a) |
325 | : "+r" (a) |
| 335 | : "r" (0x38) |
326 | : "r" (0x38) |
| Line 472... | Line 463... | ||
| 472 | "mov f123=f0\n" |
463 | "mov f123 = f0\n" |
| 473 | "mov f124=f0\n" |
464 | "mov f124 = f0\n" |
| 474 | "mov f125=f0\n" |
465 | "mov f125 = f0\n" |
| 475 | "mov f126=f0\n" |
466 | "mov f126 = f0\n" |
| 476 | "mov f127=f0\n" |
467 | "mov f127 = f0\n" |
| 477 | - | ||
| 478 | ); |
468 | ); |
| 479 | 469 | ||
| 480 | } |
470 | } |
| 481 | 471 | ||
| 482 | - | ||
| 483 | /** @} |
472 | /** @} |
| 484 | */ |
473 | */ |
| 485 | - | ||