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29 | #ifndef __ia64_ASM_H__ |
29 | #ifndef __ia64_ASM_H__ |
30 | #define __ia64_ASM_H__ |
30 | #define __ia64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
- | 34 | #include <arch/register.h> |
|
34 | 35 | ||
35 | /** Return base address of current stack |
36 | /** Return base address of current stack |
36 | * |
37 | * |
37 | * Return the base address of the current stack. |
38 | * Return the base address of the current stack. |
38 | * The stack is assumed to be STACK_SIZE long. |
39 | * The stack is assumed to be STACK_SIZE long. |
Line 45... | Line 46... | ||
45 | __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
46 | __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
46 | 47 | ||
47 | return v; |
48 | return v; |
48 | } |
49 | } |
49 | 50 | ||
50 | /** Read IVR (External Interrupt Vector Register) |
51 | /** Read IVR (External Interrupt Vector Register). |
51 | * |
52 | * |
52 | * @return Highest priority, pending, unmasked external interrupt vector. |
53 | * @return Highest priority, pending, unmasked external interrupt vector. |
53 | */ |
54 | */ |
54 | static inline __u8 read_ivr(void) |
55 | static inline __u64 ivr_read(void) |
55 | { |
56 | { |
56 | __u64 v; |
57 | __u64 v; |
57 | 58 | ||
58 | __asm__ volatile ("mov %0 = cr65\n" : "=r" (v)); |
59 | __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); |
59 | 60 | ||
- | 61 | return v; |
|
- | 62 | } |
|
- | 63 | ||
- | 64 | /** Write ITC (Interval Timer Counter) register. |
|
- | 65 | * |
|
- | 66 | * @param New counter value. |
|
- | 67 | */ |
|
- | 68 | static inline void itc_write(__u64 v) |
|
- | 69 | { |
|
- | 70 | __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
|
- | 71 | } |
|
- | 72 | ||
- | 73 | /** Read ITC (Interval Timer Counter) register. |
|
- | 74 | * |
|
- | 75 | * @return Current counter value. |
|
- | 76 | */ |
|
- | 77 | static inline __u64 itc_read(void) |
|
- | 78 | { |
|
- | 79 | __u64 v; |
|
- | 80 | ||
- | 81 | __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); |
|
- | 82 | ||
- | 83 | return v; |
|
- | 84 | } |
|
- | 85 | ||
- | 86 | /** Write ITM (Interval Timer Match) register. |
|
- | 87 | * |
|
- | 88 | * @param New match value. |
|
- | 89 | */ |
|
- | 90 | static inline void itm_write(__u64 v) |
|
- | 91 | { |
|
- | 92 | __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
|
- | 93 | } |
|
- | 94 | ||
- | 95 | /** Write ITV (Interval Timer Vector) register. |
|
- | 96 | * |
|
- | 97 | * @param New vector and masked bit. |
|
- | 98 | */ |
|
- | 99 | static inline void itv_write(__u64 v) |
|
- | 100 | { |
|
- | 101 | __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
|
- | 102 | } |
|
- | 103 | ||
- | 104 | /** Write EOI (End Of Interrupt) register. |
|
- | 105 | * |
|
- | 106 | * @param This value is ignored. |
|
- | 107 | */ |
|
- | 108 | static inline void eoi_write(__u64 v) |
|
- | 109 | { |
|
- | 110 | __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
|
- | 111 | } |
|
- | 112 | ||
- | 113 | /** Read TPR (Task Priority Register). |
|
- | 114 | * |
|
- | 115 | * @return Current value of TPR. |
|
- | 116 | */ |
|
- | 117 | static inline __u64 tpr_read(void) |
|
- | 118 | { |
|
- | 119 | __u64 v; |
|
- | 120 | ||
- | 121 | __asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); |
|
- | 122 | ||
- | 123 | return v; |
|
- | 124 | } |
|
- | 125 | ||
- | 126 | /** Write TPR (Task Priority Register). |
|
- | 127 | * |
|
- | 128 | * @param New value of TPR. |
|
- | 129 | */ |
|
- | 130 | static inline void tpr_write(__u64 v) |
|
- | 131 | { |
|
- | 132 | __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
|
- | 133 | } |
|
- | 134 | ||
- | 135 | /** Disable interrupts. |
|
- | 136 | * |
|
- | 137 | * Disable interrupts and return previous |
|
- | 138 | * value of PSR. |
|
- | 139 | * |
|
- | 140 | * @return Old interrupt priority level. |
|
- | 141 | */ |
|
- | 142 | static ipl_t interrupts_disable(void) |
|
- | 143 | { |
|
- | 144 | __u64 v; |
|
- | 145 | ||
- | 146 | __asm__ volatile ( |
|
- | 147 | "mov %0 = psr\n" |
|
- | 148 | "rsm %1\n" |
|
- | 149 | : "=r" (v) |
|
- | 150 | : "i" (PSR_I_MASK) |
|
- | 151 | ); |
|
- | 152 | ||
- | 153 | return (ipl_t) v; |
|
- | 154 | } |
|
- | 155 | ||
- | 156 | /** Enable interrupts. |
|
- | 157 | * |
|
- | 158 | * Enable interrupts and return previous |
|
- | 159 | * value of PSR. |
|
- | 160 | * |
|
- | 161 | * @return Old interrupt priority level. |
|
- | 162 | */ |
|
- | 163 | static ipl_t interrupts_enable(void) |
|
- | 164 | { |
|
- | 165 | __u64 v; |
|
- | 166 | ||
- | 167 | __asm__ volatile ( |
|
- | 168 | "mov %0 = psr\n" |
|
- | 169 | "ssm %1\n" |
|
- | 170 | ";;\n" |
|
- | 171 | "srlz.d\n" |
|
- | 172 | : "=r" (v) |
|
- | 173 | : "i" (PSR_I_MASK) |
|
- | 174 | ); |
|
- | 175 | ||
60 | return (__u8) (v & 0xf); |
176 | return (ipl_t) v; |
61 | } |
177 | } |
62 | 178 | ||
- | 179 | /** Restore interrupt priority level. |
|
- | 180 | * |
|
- | 181 | * Restore PSR. |
|
- | 182 | * |
|
- | 183 | * @param ipl Saved interrupt priority level. |
|
- | 184 | */ |
|
- | 185 | static inline void interrupts_restore(ipl_t ipl) |
|
- | 186 | { |
|
- | 187 | __asm__ volatile ( |
|
- | 188 | "mov psr.l = %0\n" |
|
- | 189 | ";;\n" |
|
- | 190 | "srlz.d\n" |
|
- | 191 | : : "r" ((__u64) ipl) |
|
- | 192 | ); |
|
- | 193 | } |
|
63 | 194 | ||
- | 195 | /** Return interrupt priority level. |
|
- | 196 | * |
|
- | 197 | * @return PSR. |
|
- | 198 | */ |
|
64 | void cpu_sleep(void); |
199 | static inline ipl_t interrupts_read(void) |
- | 200 | { |
|
- | 201 | __u64 v; |
|
65 | 202 | ||
66 | void asm_delay_loop(__u32 t); |
203 | __asm__ volatile ("mov %0 = psr\n" : "=r" (v)); |
67 | 204 | ||
- | 205 | return (ipl_t) v; |
|
- | 206 | } |
|
68 | 207 | ||
69 | #define set_shadow_register(reg,val) {__u64 v = val; __asm__ volatile("mov r15 = %0;;\n""bsw.0;;\n""mov " #reg " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); } |
208 | #define set_shadow_register(reg,val) {__u64 v = val; __asm__ volatile("mov r15 = %0;;\n""bsw.0;;\n""mov " #reg " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); } |
70 | #define get_shadow_register(reg,val) {__u64 v ; __asm__ volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
209 | #define get_shadow_register(reg,val) {__u64 v ; __asm__ volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
71 | 210 | ||
72 | #define get_control_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
211 | #define get_control_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
73 | #define get_aplication_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
212 | #define get_aplication_register(reg,val) {__u64 v ; __asm__ volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
74 | #define get_psr(val) {__u64 v ; __asm__ volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
213 | #define get_psr(val) {__u64 v ; __asm__ volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; } |
75 | 214 | ||
76 | - | ||
77 | void cpu_halt(void); |
215 | extern void cpu_halt(void); |
78 | - | ||
79 | - | ||
80 | - | ||
- | 216 | extern void cpu_sleep(void); |
|
- | 217 | extern void asm_delay_loop(__u32 t); |
|
81 | 218 | ||
82 | #endif |
219 | #endif |