WebSVN – HelenOS – Diff – /trunk/kernel/arch/arm32/src/mm/page_fault.c



#include <mm/as.h>
#include <genarch/mm/page_pt.h>
#include <arch.h>
#include <interrupt.h>
 
 
/** Returns value stored in fault status register.
 *
 *  @return Value stored in CP15 fault status register (FSR).
 */
static inline fault_status_t read_fault_status_register(void)
{
    fault_status_union_t fsu;
 
    /* fault status is stored in CP15 register 5 */
    asm volatile (
        "mrc p15, 0, %0, c5, c0, 0"
        : "=r"(fsu.dummy)
    );
    return fsu.fs;
}
 
 
/** Returns FAR (fault address register) content.
 *
 * @return FAR (fault address register) content (address that caused a page
 *     fault)
 */
static inline uintptr_t read_fault_address_register(void)
{
    uintptr_t ret;
 
    /* fault adress is stored in CP15 register 6 */
    asm volatile (
        "mrc p15, 0, %0, c6, c0, 0"
        : "=r"(ret)
    );
    return ret;
}
 
 
/** Decides whether the instruction is load/store or not.
 *
 * @param instr Instruction
 *
 * @return true when instruction is load/store, false otherwise
 */
static inline bool is_load_store_instruction(instruction_t instr)
{
    /* load store immediate offset */
    if (instr.type == 0x2) {
        return true;
    }
 
    /* load store register offset */
    if (instr.type == 0x3 && instr.bit4 == 0) {
        return true;
    }
 
    /* load store multiple */
    if (instr.type == 0x4) {
        return true;
    }
 
    /* oprocessor load/store */
    if (instr.type == 0x6) {
        return true;
    }
 
    return false;
}
 
 
/** Decides whether the instruction is swap or not.
 *
 * @param instr Instruction
 *
 * @return true when instruction is swap, false otherwise
 */
static inline bool is_swap_instruction(instruction_t instr)
{
    /* swap, swapb instruction */
    if (instr.type == 0x0 &&
        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
        return true;
    }
 
    return false;
}
 
 
/** Decides whether read or write into memory is requested.
 *
 * @param instr_addr   Address of instruction which tries to access memory.
 * @param badvaddr     Virtual address the instruction tries to access.
 *
 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
 *     requested.
 */
static pf_access_t get_memory_access_type(uint32_t instr_addr,
    uintptr_t badvaddr)
{
    instruction_union_t instr_union;
    instr_union.pc = instr_addr;
 
    instruction_t instr = *(instr_union.instr);
 
    /* undefined instructions */
    if (instr.condition == 0xf) {
        panic("page_fault - instruction doesn't access memory "
            "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
        return PF_ACCESS_EXEC;
    }
 
    /* load store instructions */
    if (is_load_store_instruction(instr)) {
        if (instr.access == 1) {
            return PF_ACCESS_READ;
        } else {
            return PF_ACCESS_WRITE;
        }
    }
 
    /* swap, swpb instruction */
    if (is_swap_instruction(instr)) {
        return PF_ACCESS_WRITE;
    }
 
    panic("page_fault - instruction doesn't access memory "
        "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
 
    return PF_ACCESS_EXEC;
}
 
/** Handles "data abort" exception (load or store at invalid address).

 
    int ret = as_page_fault(badvaddr, access, istate);
 
    if (ret == AS_PF_FAULT) {
        print_istate(istate);
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
            "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
            access);
 
        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
        panic("page fault\n");
    }
}

    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
 
    if (ret == AS_PF_FAULT) {
        dprintf("prefetch_abort\n");
        print_istate(istate);
        panic("page fault - prefetch_abort at address: %x\n",
            istate->pc);
    }
}
 
/** @}
 */
 

Rev 2418	Rev 2464
Line 39...	Line 39...
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <genarch/mm/page_pt.h>	40	#include <genarch/mm/page_pt.h>
41	#include <arch.h>	41	#include <arch.h>
42	#include <interrupt.h>	42	#include <interrupt.h>
43		43
44		-
45	/** Returns value stored in fault status register.	44	/** Returns value stored in fault status register.
46	*	45	*
47	* @return Value stored in CP15 fault status register (FSR).	46	* @return Value stored in CP15 fault status register (FSR).
48	*/	47	*/
49	static inline fault_status_t read_fault_status_register(void)	48	static inline fault_status_t read_fault_status_register(void)
50	{	49	{
51	fault_status_union_t fsu;	50	fault_status_union_t fsu;
52		51
53	// fault status is stored in CP15 register 5	52	/* fault status is stored in CP15 register 5 */
54	asm volatile (	53	asm volatile (
55	"mrc p15, 0, %0, c5, c0, 0"	54	"mrc p15, 0, %0, c5, c0, 0"
56	: "=r"(fsu.dummy)	55	: "=r"(fsu.dummy)
57	);	56	);
58	return fsu.fs;	57	return fsu.fs;
59	}	58	}
60		59
61		-
62	/** Returns FAR (fault address register) content.	60	/** Returns FAR (fault address register) content.
63	*	61	*
64	* @return FAR (fault address register) content (address that caused a page fault)	62	* @return FAR (fault address register) content (address that caused a page
-		63	* fault)
65	*/	64	*/
66	static inline uintptr_t read_fault_address_register(void)	65	static inline uintptr_t read_fault_address_register(void)
67	{	66	{
68	uintptr_t ret;	67	uintptr_t ret;
69		68
70	// fault adress is stored in CP15 register 6	69	/* fault adress is stored in CP15 register 6 */
71	asm volatile (	70	asm volatile (
72	"mrc p15, 0, %0, c6, c0, 0"	71	"mrc p15, 0, %0, c6, c0, 0"
73	: "=r"(ret)	72	: "=r"(ret)
74	);	73	);
75	return ret;	74	return ret;
76	}	75	}
77		76
78		-
79	/** Decides whether the instruction is load/store or not.	77	/** Decides whether the instruction is load/store or not.
80	*	78	*
81	* @param instr Instruction	79	* @param instr Instruction
82	*	80	*
83	* @return true when instruction is load/store, false otherwise	81	* @return true when instruction is load/store, false otherwise
84	*/	82	*/
85	static inline bool is_load_store_instruction(instruction_t instr)	83	static inline bool is_load_store_instruction(instruction_t instr)
86	{	84	{
87	// load store immediate offset	85	/* load store immediate offset */
88	if (instr.type == 0x2) {	86	if (instr.type == 0x2) {
89	return true;	87	return true;
90	}	88	}
91		89
92	// load store register offset	90	/* load store register offset */
93	if (instr.type == 0x3 && instr.bit4 == 0) {	91	if (instr.type == 0x3 && instr.bit4 == 0) {
94	return true;	92	return true;
95	}	93	}
96		94
97	// load store multiple	95	/* load store multiple */
98	if (instr.type == 0x4) {	96	if (instr.type == 0x4) {
99	return true;	97	return true;
100	}	98	}
101		99
102	// coprocessor load/store	100	/* oprocessor load/store */
103	if (instr.type == 0x6) {	101	if (instr.type == 0x6) {
104	return true;	102	return true;
105	}	103	}
106		104
107	return false;	105	return false;
108	}	106	}
109		107
110		-
111	/** Decides whether the instructions is swap or not.	108	/** Decides whether the instruction is swap or not.
112	*	109	*
113	* @param instr Instruction	110	* @param instr Instruction
114	*	111	*
115	* @return true when instruction is swap, false otherwise	112	* @return true when instruction is swap, false otherwise
116	*/	113	*/
117	static inline bool is_swap_instruction(instruction_t instr)	114	static inline bool is_swap_instruction(instruction_t instr)
118	{	115	{
119	// swap, swapb instruction	116	/* swap, swapb instruction */
120	if (instr.type == 0x0 &&	117	if (instr.type == 0x0 &&
121	(instr.opcode == 0x8 \|\| instr.opcode == 0xa) &&	118	(instr.opcode == 0x8 \|\| instr.opcode == 0xa) &&
122	instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {	119	instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
123	return true;	120	return true;
124	}	121	}
125		122
126	return false;	123	return false;
127	}	124	}
128		125
129		-
130	/** Decides whether read or write into memory is requested.	126	/** Decides whether read or write into memory is requested.
131	*	127	*
132	* @param instr_addr Address of instruction which tries to access memory.	128	* @param instr_addr Address of instruction which tries to access memory.
133	* @param badvaddr Virtual address the instruction tries to access.	129	* @param badvaddr Virtual address the instruction tries to access.
134	*	130	*
135	* @return Type of access into memory, PF_ACCESS_EXEC if no memory access is requested.	131	* @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
-		132	* requested.
136	*/	133	*/
137	static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)	134	static pf_access_t get_memory_access_type(uint32_t instr_addr,
-		135	uintptr_t badvaddr)
138	{	136	{
139	instruction_union_t instr_union;	137	instruction_union_t instr_union;
140	instr_union.pc = instr_addr;	138	instr_union.pc = instr_addr;
141		139
142	instruction_t instr = *(instr_union.instr);	140	instruction_t instr = *(instr_union.instr);
143		141
144	// undefined instructions	142	/* undefined instructions */
145	if (instr.condition == 0xf) {	143	if (instr.condition == 0xf) {
146	panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",	144	panic("page_fault - instruction doesn't access memory "
147	instr, badvaddr);	145	"(instr_code: %x, badvaddr:%x)", instr, badvaddr);
148	return PF_ACCESS_EXEC;	146	return PF_ACCESS_EXEC;
149	}	147	}
150		148
151	// load store instructions	149	/* load store instructions */
152	if (is_load_store_instruction(instr)) {	150	if (is_load_store_instruction(instr)) {
153	if (instr.access == 1) {	151	if (instr.access == 1) {
154	return PF_ACCESS_READ;	152	return PF_ACCESS_READ;
155	} else {	153	} else {
156	return PF_ACCESS_WRITE;	154	return PF_ACCESS_WRITE;
157	}	155	}
158	}	156	}
159		157
160	// swap, swpb instruction	158	/* swap, swpb instruction */
161	if (is_swap_instruction(instr)) {	159	if (is_swap_instruction(instr)) {
162	return PF_ACCESS_WRITE;	160	return PF_ACCESS_WRITE;
163	}	161	}
164		162
165	panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",	163	panic("page_fault - instruction doesn't access memory "
166	instr, badvaddr);	164	"(instr_code: %x, badvaddr:%x)", instr, badvaddr);
167		165
168	return PF_ACCESS_EXEC;	166	return PF_ACCESS_EXEC;
169	}	167	}
170		168
171	/** Handles "data abort" exception (load or store at invalid address).	169	/** Handles "data abort" exception (load or store at invalid address).
Line 182...	Line 180...
182		180
183	int ret = as_page_fault(badvaddr, access, istate);	181	int ret = as_page_fault(badvaddr, access, istate);
184		182
185	if (ret == AS_PF_FAULT) {	183	if (ret == AS_PF_FAULT) {
186	print_istate(istate);	184	print_istate(istate);
187	dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",	185	dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
188	istate->pc, badvaddr, fsr.status, fsr, access);	186	"access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
-		187	access);
189		188
190	fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);	189	fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
191	panic("page fault\n");	190	panic("page fault\n");
192	}	191	}
193	}	192	}
Line 202...	Line 201...
202	int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);	201	int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
203		202
204	if (ret == AS_PF_FAULT) {	203	if (ret == AS_PF_FAULT) {
205	dprintf("prefetch_abort\n");	204	dprintf("prefetch_abort\n");
206	print_istate(istate);	205	print_istate(istate);
207	panic("page fault - prefetch_abort at address: %x\n", istate->pc);	206	panic("page fault - prefetch_abort at address: %x\n",
-		207	istate->pc);
208	}	208	}
209	}	209	}
210		210
211	/** @}	211	/** @}
212	*/	212	*/
213		-

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/arm32/src/mm/page_fault.c @ 2465 – Rev 2418 → 2464