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53 | # define PA2KA(x) ((x) + 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
54 | #endif |
54 | #endif |
55 | 55 | ||
56 | #ifdef KERNEL |
56 | #ifdef KERNEL |
57 | 57 | ||
- | 58 | /* Number of entries in each level. */ |
|
58 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
59 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
59 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
61 | #define PTL2_ENTRIES_ARCH 0 |
61 | - | ||
62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
64 | 64 | ||
- | 65 | /* Page table sizes for each level. */ |
|
65 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
66 | #define PTL1_SIZE_ARCH 0 |
67 | #define PTL1_SIZE_ARCH 0 |
67 | #define PTL2_SIZE_ARCH 0 |
68 | #define PTL2_SIZE_ARCH 0 |
68 | #define PTL3_SIZE_ARCH ONE_FRAME |
69 | #define PTL3_SIZE_ARCH ONE_FRAME |
69 | 70 | ||
- | 71 | /* Macros calculating indices into page tables for each level. */ |
|
70 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
72 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
71 | #define PTL1_INDEX_ARCH(vaddr) 0 |
73 | #define PTL1_INDEX_ARCH(vaddr) 0 |
72 | #define PTL2_INDEX_ARCH(vaddr) 0 |
74 | #define PTL2_INDEX_ARCH(vaddr) 0 |
73 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
75 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
74 | 76 | ||
- | 77 | /* Get PTE address accessors for each level. */ |
|
75 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
78 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
76 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
79 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
77 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
80 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
78 | (ptl1) |
81 | (ptl1) |
79 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
82 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
80 | (ptl2) |
83 | (ptl2) |
81 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
84 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
82 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
85 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
83 | 86 | ||
- | 87 | /* Set PTE address accessors for each level. */ |
|
84 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
88 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
85 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
89 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
86 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
90 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
87 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
91 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
88 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
92 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
89 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
93 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
90 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
94 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
91 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
95 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
92 | 96 | ||
- | 97 | /* Get PTE flags accessors for each level. */ |
|
93 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
98 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
94 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
99 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
95 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
100 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
96 | PAGE_PRESENT |
101 | PAGE_PRESENT |
97 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
102 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
98 | PAGE_PRESENT |
103 | PAGE_PRESENT |
99 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
104 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
100 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
105 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
101 | 106 | ||
- | 107 | /* Set PTE flags accessors for each level. */ |
|
102 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
108 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
103 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
109 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
104 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
110 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
105 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
111 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
106 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
112 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
107 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
113 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
108 | 114 | ||
- | 115 | /* Macros for querying the last-level PTE entries. */ |
|
109 | #define PTE_VALID_ARCH(pte) \ |
116 | #define PTE_VALID_ARCH(pte) \ |
110 | (*((uint32_t *) (pte)) != 0) |
117 | (*((uint32_t *) (pte)) != 0) |
111 | #define PTE_PRESENT_ARCH(pte) \ |
118 | #define PTE_PRESENT_ARCH(pte) \ |
112 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
119 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
113 | - | ||
114 | /* pte should point into ptl3 */ |
- | |
115 | #define PTE_GET_FRAME_ARCH(pte) \ |
120 | #define PTE_GET_FRAME_ARCH(pte) \ |
116 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
121 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
117 | - | ||
118 | /* pte should point into ptl3 */ |
- | |
119 | #define PTE_WRITABLE_ARCH(pte) \ |
122 | #define PTE_WRITABLE_ARCH(pte) \ |
120 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
123 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
121 | PTE_AP_USER_RW_KERNEL_RW) |
124 | PTE_AP_USER_RW_KERNEL_RW) |
122 | - | ||
123 | #define PTE_EXECUTABLE_ARCH(pte) \ |
125 | #define PTE_EXECUTABLE_ARCH(pte) \ |
124 | 1 |
126 | 1 |
125 | 127 | ||
126 | #ifndef __ASM__ |
128 | #ifndef __ASM__ |
127 | 129 |