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29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
33 | 33 | ||
- | 34 | /** I-MMU ASIs. */ |
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- | 35 | #define ASI_IMMU 0x50 |
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- | 36 | #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
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- | 37 | #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
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- | 38 | #define ASI_ITLB_DATA_IN_REG 0x54 |
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- | 39 | #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
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- | 40 | #define ASI_ITLB_TAG_READ_REG 0x56 |
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- | 41 | #define ASI_IMMU_DEMAP 0x57 |
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- | 42 | ||
- | 43 | /** Virtual Addresses within ASI_IMMU. */ |
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- | 44 | #define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */ |
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- | 45 | #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
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- | 46 | #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
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- | 47 | #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
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- | 48 | ||
- | 49 | /** D-MMU ASIs. */ |
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- | 50 | #define ASI_DMMU 0x58 |
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- | 51 | #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
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- | 52 | #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
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- | 53 | #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
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- | 54 | #define ASI_DTLB_DATA_IN_REG 0x5c |
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- | 55 | #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
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- | 56 | #define ASI_DTLB_TAG_READ_REG 0x5e |
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- | 57 | #define ASI_DMMU_DEMAP 0x5f |
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- | 58 | ||
- | 59 | /** Virtual Addresses within ASI_DMMU. */ |
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- | 60 | #define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */ |
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- | 61 | #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
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- | 62 | #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
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- | 63 | #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
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- | 64 | #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
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- | 65 | #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
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- | 66 | #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
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- | 67 | #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
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- | 68 | #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
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- | 69 | ||
34 | /** I-/D-TLB Data In/Access Register type. */ |
70 | /** I-/D-TLB Data In/Access Register type. */ |
35 | typedef tte_data_t tlb_data_t; |
71 | typedef tte_data_t tlb_data_t; |
36 | 72 | ||
37 | #define tlb_init_arch() |
73 | #define tlb_init_arch() |
38 | 74 |