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 */
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 */
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#include <arch/mm/tlb.h>
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#include <arch/mm/tlb.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <mm/tlb.h>
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#include <mm/tlb.h>
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#include <mm/frame.h>
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#include <mm/page.h>
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#include <mm/page.h>
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#include <mm/as.h>
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#include <mm/as.h>
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#include <arch.h>
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#include <arch.h>
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#include <print.h>
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#include <print.h>
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#include <symtab.h>
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#include <symtab.h>
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static phte_t *phte;
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/** Initialize Page Hash Table.
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/** Initialize Page Hash Table.
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 *
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 *
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 * Setup the Page Hash Table with no entries.
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 * Setup the Page Hash Table with no entries.
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 *
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 *
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 */
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 */
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void tlb_arch_init(void)
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void tlb_arch_init(void)
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{
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{
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    phte_t *physical_phte = (phte_t *) PFN2ADDR(frame_alloc(PHT_ORDER, FRAME_KA | FRAME_PANIC));
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    phte =(phte_t *) PA2KA((__address) physical_phte);
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    ASSERT((__address) physical_phte % (1 << PHT_BITS) == 0);
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    memsetb((__address) phte, 1 << PHT_BITS, 0);
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    asm volatile (
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        "mtsdr1 %0\n"
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        :
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        : "r" ((__address) physical_phte)
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    );
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}
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}
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/** Try to find PTE for faulting address
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/** Try to find PTE for faulting address
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 *
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 *
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    if (s)
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    if (s)
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        symbol = s;
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        symbol = s;
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    s = get_symtab_entry(istate->lr);
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    s = get_symtab_entry(istate->lr);
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    if (s)
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    if (s)
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        sym2 = s;
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        sym2 = s;
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    panic("%X: PHT Refill Exception at %X(%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
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    panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
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}
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}
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/** Process Data Storage Interrupt
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/** Process Instruction/Data Storage Interrupt
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 *
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 *
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 * @param data   True if Data Storage Interrupt.
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 * @param istate Interrupted register context.
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 * @param istate Interrupted register context.
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 *
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 *
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 */
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 */
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void pht_refill(istate_t *istate)
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void pht_refill(bool data, istate_t *istate)
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{
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{
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    asid_t asid;
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    asid_t asid;
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    __address badvaddr;
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    __address badvaddr;
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    pte_t *pte;
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    pte_t *pte;
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    __u32 page;
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    __u32 api;
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    __u32 vsid;
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    __u32 hash;
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    __u32 i;
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    if (data) {
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    __asm__ volatile (
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        asm volatile (
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        "mfdar %0\n"
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            "mfdar %0\n"
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        : "=r" (badvaddr)
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            : "=r" (badvaddr)
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    );
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        );
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    } else
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        badvaddr = istate->pc;
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    spinlock_lock(&AS->lock);
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    spinlock_lock(&AS->lock);
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    asid = AS->asid;
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    asid = AS->asid;
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    spinlock_unlock(&AS->lock);
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    spinlock_unlock(&AS->lock);
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132
    pte = find_mapping_and_check(badvaddr);
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    pte = find_mapping_and_check(badvaddr);
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    if (!pte)
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    if (!pte)
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        goto fail;
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        goto fail;
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160
 
136
    /*
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     * Record access to PTE.
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    /* Record access to PTE */
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     */
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    pte->a = 1;
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    pte->a = 1;
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    page = ADDR2PFN(badvaddr);
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    api = (badvaddr >> 22) & 0x3f;
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    asm volatile (
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        "mfsrin %0, %1\n"
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        : "=r" (vsid)
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        : "r" (badvaddr >> 28)
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170
    );
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171
   
-
 
172
    /* Primary hash (xor) */
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173
    hash = ((vsid ^ page) & 0x3ff) << 3;
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174
   
141
    // FIXME: Insert entry into PHT
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    /* Find invalid PTE in PTEG */
-
 
176
    for (i = 0; i < 8; i++) {
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177
        if (!phte[hash + i].v)
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            break;
-
 
179
    }
-
 
180
   
-
 
181
    // TODO: Check access/change bits, secondary hash
-
 
182
   
-
 
183
    if (i == 8)
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184
        i = page % 8;
-
 
185
   
-
 
186
    phte[hash + i].v = 1;
-
 
187
    phte[hash + i].vsid = vsid;
-
 
188
    phte[hash + i].h = 0;
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189
    phte[hash + i].api = api;
-
 
190
    phte[hash + i].rpn = pte->pfn;
-
 
191
    phte[hash + i].r = 0;
-
 
192
    phte[hash + i].c = 0;
-
 
193
    phte[hash + i].pp = 2; // FIXME
142
 
194
   
143
    page_table_unlock(AS, true);
195
    page_table_unlock(AS, true);
144
    return;
196
    return;
145
   
197
   
146
fail:
198
fail: