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33 | 33 | ||
34 | #define cp0_status_ie_enabled_bit (1<<0) |
34 | #define cp0_status_ie_enabled_bit (1<<0) |
35 | #define cp0_status_exl_exception_bit (1<<1) |
35 | #define cp0_status_exl_exception_bit (1<<1) |
36 | #define cp0_status_erl_error_bit (1<<2) |
36 | #define cp0_status_erl_error_bit (1<<2) |
37 | #define cp0_status_bev_bootstrap_bit (1<<22) |
37 | #define cp0_status_bev_bootstrap_bit (1<<22) |
- | 38 | #define cp0_status_um_bit (1<<4) |
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38 | 39 | ||
39 | #define cp0_status_im7_shift 15 |
40 | #define cp0_status_im7_shift 15 |
40 | /* |
41 | /* |
41 | * Magic value for use in msim. |
42 | * Magic value for use in msim. |
42 | * On AMD Duron 800Mhz, this roughly seems like one us. |
43 | * On AMD Duron 800Mhz, this roughly seems like one us. |