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}
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}
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/** Instruction TLB fault handler for faults with VHPT turned off.
442
/** Instruction TLB fault handler for faults with VHPT turned off.
443
 *
443
 *
444
 * @param vector Interruption vector.
444
 * @param vector Interruption vector.
445
 * @param pstate Structure with saved interruption state.
445
 * @param istate Structure with saved interruption state.
446
 */
446
 */
447
void alternate_instruction_tlb_fault(__u64 vector, struct exception_regdump *pstate)
447
void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
448
{
448
{
449
    region_register rr;
449
    region_register rr;
450
    __address va;
450
    __address va;
451
    pte_t *t;
451
    pte_t *t;
452
   
452
   
453
    va = pstate->cr_ifa;    /* faulting address */
453
    va = istate->cr_ifa;    /* faulting address */
454
    t = page_mapping_find(AS, va);
454
    t = page_mapping_find(AS, va);
455
    if (t) {
455
    if (t) {
456
        /*
456
        /*
457
         * The mapping was found in software page hash table.
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         * The mapping was found in software page hash table.
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         * Insert it into data translation cache.
458
         * Insert it into data translation cache.
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461
    } else {
461
    } else {
462
        /*
462
        /*
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         * Forward the page fault to address space page fault handler.
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         * Forward the page fault to address space page fault handler.
464
         */
464
         */
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        if (!as_page_fault(va)) {
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        if (!as_page_fault(va)) {
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            panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
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            panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
467
        }
467
        }
468
    }
468
    }
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}
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}
470
 
470
 
471
/** Data TLB fault handler for faults with VHPT turned off.
471
/** Data TLB fault handler for faults with VHPT turned off.
472
 *
472
 *
473
 * @param vector Interruption vector.
473
 * @param vector Interruption vector.
474
 * @param pstate Structure with saved interruption state.
474
 * @param istate Structure with saved interruption state.
475
 */
475
 */
476
void alternate_data_tlb_fault(__u64 vector, struct exception_regdump *pstate)
476
void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
477
{
477
{
478
    region_register rr;
478
    region_register rr;
479
    rid_t rid;
479
    rid_t rid;
480
    __address va;
480
    __address va;
481
    pte_t *t;
481
    pte_t *t;
482
   
482
   
483
    va = pstate->cr_ifa;    /* faulting address */
483
    va = istate->cr_ifa;    /* faulting address */
484
    rr.word = rr_read(VA2VRN(va));
484
    rr.word = rr_read(VA2VRN(va));
485
    rid = rr.map.rid;
485
    rid = rr.map.rid;
486
    if (RID2ASID(rid) == ASID_KERNEL) {
486
    if (RID2ASID(rid) == ASID_KERNEL) {
487
        if (VA2VRN(va) == VRN_KERNEL) {
487
        if (VA2VRN(va) == VRN_KERNEL) {
488
            /*
488
            /*
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    } else {
504
    } else {
505
        /*
505
        /*
506
         * Forward the page fault to address space page fault handler.
506
         * Forward the page fault to address space page fault handler.
507
         */
507
         */
508
        if (!as_page_fault(va)) {
508
        if (!as_page_fault(va)) {
509
            panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
509
            panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
510
        }
510
        }
511
    }
511
    }
512
}
512
}
513
 
513
 
514
/** Data nested TLB fault handler.
514
/** Data nested TLB fault handler.
515
 *
515
 *
516
 * This fault should not occur.
516
 * This fault should not occur.
517
 *
517
 *
518
 * @param vector Interruption vector.
518
 * @param vector Interruption vector.
519
 * @param pstate Structure with saved interruption state.
519
 * @param istate Structure with saved interruption state.
520
 */
520
 */
521
void data_nested_tlb_fault(__u64 vector, struct exception_regdump *pstate)
521
void data_nested_tlb_fault(__u64 vector, istate_t *istate)
522
{
522
{
523
    panic("%s\n", __FUNCTION__);
523
    panic("%s\n", __FUNCTION__);
524
}
524
}
525
 
525
 
526
/** Data Dirty bit fault handler.
526
/** Data Dirty bit fault handler.
527
 *
527
 *
528
 * @param vector Interruption vector.
528
 * @param vector Interruption vector.
529
 * @param pstate Structure with saved interruption state.
529
 * @param istate Structure with saved interruption state.
530
 */
530
 */
531
void data_dirty_bit_fault(__u64 vector, struct exception_regdump *pstate)
531
void data_dirty_bit_fault(__u64 vector, istate_t *istate)
532
{
532
{
533
    pte_t *t;
533
    pte_t *t;
534
 
534
 
535
    t = page_mapping_find(AS, pstate->cr_ifa);
535
    t = page_mapping_find(AS, istate->cr_ifa);
536
    ASSERT(t && t->p);
536
    ASSERT(t && t->p);
537
    if (t && t->p) {
537
    if (t && t->p) {
538
        /*
538
        /*
539
         * Update the Dirty bit in page tables and reinsert
539
         * Update the Dirty bit in page tables and reinsert
540
         * the mapping into DTC.
540
         * the mapping into DTC.
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545
}
545
}
546
 
546
 
547
/** Instruction access bit fault handler.
547
/** Instruction access bit fault handler.
548
 *
548
 *
549
 * @param vector Interruption vector.
549
 * @param vector Interruption vector.
550
 * @param pstate Structure with saved interruption state.
550
 * @param istate Structure with saved interruption state.
551
 */
551
 */
552
void instruction_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
552
void instruction_access_bit_fault(__u64 vector, istate_t *istate)
553
{
553
{
554
    pte_t *t;
554
    pte_t *t;
555
 
555
 
556
    t = page_mapping_find(AS, pstate->cr_ifa);
556
    t = page_mapping_find(AS, istate->cr_ifa);
557
    ASSERT(t && t->p);
557
    ASSERT(t && t->p);
558
    if (t && t->p) {
558
    if (t && t->p) {
559
        /*
559
        /*
560
         * Update the Accessed bit in page tables and reinsert
560
         * Update the Accessed bit in page tables and reinsert
561
         * the mapping into ITC.
561
         * the mapping into ITC.
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566
}
566
}
567
 
567
 
568
/** Data access bit fault handler.
568
/** Data access bit fault handler.
569
 *
569
 *
570
 * @param vector Interruption vector.
570
 * @param vector Interruption vector.
571
 * @param pstate Structure with saved interruption state.
571
 * @param istate Structure with saved interruption state.
572
 */
572
 */
573
void data_access_bit_fault(__u64 vector, struct exception_regdump *pstate)
573
void data_access_bit_fault(__u64 vector, istate_t *istate)
574
{
574
{
575
    pte_t *t;
575
    pte_t *t;
576
 
576
 
577
    t = page_mapping_find(AS, pstate->cr_ifa);
577
    t = page_mapping_find(AS, istate->cr_ifa);
578
    ASSERT(t && t->p);
578
    ASSERT(t && t->p);
579
    if (t && t->p) {
579
    if (t && t->p) {
580
        /*
580
        /*
581
         * Update the Accessed bit in page tables and reinsert
581
         * Update the Accessed bit in page tables and reinsert
582
         * the mapping into DTC.
582
         * the mapping into DTC.
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587
}
587
}
588
 
588
 
589
/** Page not present fault handler.
589
/** Page not present fault handler.
590
 *
590
 *
591
 * @param vector Interruption vector.
591
 * @param vector Interruption vector.
592
 * @param pstate Structure with saved interruption state.
592
 * @param istate Structure with saved interruption state.
593
 */
593
 */
594
void page_not_present(__u64 vector, struct exception_regdump *pstate)
594
void page_not_present(__u64 vector, istate_t *istate)
595
{
595
{
596
    region_register rr;
596
    region_register rr;
597
    __address va;
597
    __address va;
598
    pte_t *t;
598
    pte_t *t;
599
   
599
   
600
    va = pstate->cr_ifa;    /* faulting address */
600
    va = istate->cr_ifa;    /* faulting address */
601
    t = page_mapping_find(AS, va);
601
    t = page_mapping_find(AS, va);
602
    ASSERT(t);
602
    ASSERT(t);
603
   
603
   
604
    if (t->p) {
604
    if (t->p) {
605
        /*
605
        /*
Line 610... Line 610...
610
            itc_pte_copy(t);
610
            itc_pte_copy(t);
611
        else
611
        else
612
            dtc_pte_copy(t);
612
            dtc_pte_copy(t);
613
    } else {
613
    } else {
614
        if (!as_page_fault(va)) {
614
        if (!as_page_fault(va)) {
615
            panic("%s: va=%P, rid=%d\n", __FUNCTION__, pstate->cr_ifa, rr.map.rid);
615
            panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
616
        }
616
        }
617
    }
617
    }
618
}
618
}