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Rev 1735 | Rev 1780 | ||
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Line 55... | Line 55... | ||
55 | 55 | ||
56 | /** Invalidate all TLB entries. */ |
56 | /** Invalidate all TLB entries. */ |
57 | void tlb_invalidate_all(void) |
57 | void tlb_invalidate_all(void) |
58 | { |
58 | { |
59 | ipl_t ipl; |
59 | ipl_t ipl; |
60 | __address adr; |
60 | uintptr_t adr; |
61 | __u32 count1, count2, stride1, stride2; |
61 | uint32_t count1, count2, stride1, stride2; |
62 | 62 | ||
63 | int i,j; |
63 | int i,j; |
64 | 64 | ||
65 | adr = PAL_PTCE_INFO_BASE(); |
65 | adr = PAL_PTCE_INFO_BASE(); |
66 | count1 = PAL_PTCE_INFO_COUNT1(); |
66 | count1 = PAL_PTCE_INFO_COUNT1(); |
Line 99... | Line 99... | ||
99 | { |
99 | { |
100 | tlb_invalidate_all(); |
100 | tlb_invalidate_all(); |
101 | } |
101 | } |
102 | 102 | ||
103 | 103 | ||
104 | void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt) |
104 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
105 | { |
105 | { |
106 | region_register rr; |
106 | region_register rr; |
107 | bool restore_rr = false; |
107 | bool restore_rr = false; |
108 | int b = 0; |
108 | int b = 0; |
109 | int c = cnt; |
109 | int c = cnt; |
110 | 110 | ||
111 | __address va; |
111 | uintptr_t va; |
112 | va = page; |
112 | va = page; |
113 | 113 | ||
114 | rr.word = rr_read(VA2VRN(va)); |
114 | rr.word = rr_read(VA2VRN(va)); |
115 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
115 | if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) { |
116 | /* |
116 | /* |
Line 127... | Line 127... | ||
127 | } |
127 | } |
128 | 128 | ||
129 | while(c >>= 1) |
129 | while(c >>= 1) |
130 | b++; |
130 | b++; |
131 | b >>= 1; |
131 | b >>= 1; |
132 | __u64 ps; |
132 | uint64_t ps; |
133 | 133 | ||
134 | switch (b) { |
134 | switch (b) { |
135 | case 0: /*cnt 1-3*/ |
135 | case 0: /*cnt 1-3*/ |
136 | ps = PAGE_WIDTH; |
136 | ps = PAGE_WIDTH; |
137 | break; |
137 | break; |
Line 199... | Line 199... | ||
199 | * |
199 | * |
200 | * @param va Virtual page address. |
200 | * @param va Virtual page address. |
201 | * @param asid Address space identifier. |
201 | * @param asid Address space identifier. |
202 | * @param entry The rest of TLB entry as required by TLB insertion format. |
202 | * @param entry The rest of TLB entry as required by TLB insertion format. |
203 | */ |
203 | */ |
204 | void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) |
204 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
205 | { |
205 | { |
206 | tc_mapping_insert(va, asid, entry, true); |
206 | tc_mapping_insert(va, asid, entry, true); |
207 | } |
207 | } |
208 | 208 | ||
209 | /** Insert data into instruction translation cache. |
209 | /** Insert data into instruction translation cache. |
210 | * |
210 | * |
211 | * @param va Virtual page address. |
211 | * @param va Virtual page address. |
212 | * @param asid Address space identifier. |
212 | * @param asid Address space identifier. |
213 | * @param entry The rest of TLB entry as required by TLB insertion format. |
213 | * @param entry The rest of TLB entry as required by TLB insertion format. |
214 | */ |
214 | */ |
215 | void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry) |
215 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
216 | { |
216 | { |
217 | tc_mapping_insert(va, asid, entry, false); |
217 | tc_mapping_insert(va, asid, entry, false); |
218 | } |
218 | } |
219 | 219 | ||
220 | /** Insert data into instruction or data translation cache. |
220 | /** Insert data into instruction or data translation cache. |
Line 222... | Line 222... | ||
222 | * @param va Virtual page address. |
222 | * @param va Virtual page address. |
223 | * @param asid Address space identifier. |
223 | * @param asid Address space identifier. |
224 | * @param entry The rest of TLB entry as required by TLB insertion format. |
224 | * @param entry The rest of TLB entry as required by TLB insertion format. |
225 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
225 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
226 | */ |
226 | */ |
227 | void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc) |
227 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
228 | { |
228 | { |
229 | region_register rr; |
229 | region_register rr; |
230 | bool restore_rr = false; |
230 | bool restore_rr = false; |
231 | 231 | ||
232 | rr.word = rr_read(VA2VRN(va)); |
232 | rr.word = rr_read(VA2VRN(va)); |
Line 273... | Line 273... | ||
273 | * @param va Virtual page address. |
273 | * @param va Virtual page address. |
274 | * @param asid Address space identifier. |
274 | * @param asid Address space identifier. |
275 | * @param entry The rest of TLB entry as required by TLB insertion format. |
275 | * @param entry The rest of TLB entry as required by TLB insertion format. |
276 | * @param tr Translation register. |
276 | * @param tr Translation register. |
277 | */ |
277 | */ |
278 | void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
278 | void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
279 | { |
279 | { |
280 | tr_mapping_insert(va, asid, entry, false, tr); |
280 | tr_mapping_insert(va, asid, entry, false, tr); |
281 | } |
281 | } |
282 | 282 | ||
283 | /** Insert data into data translation register. |
283 | /** Insert data into data translation register. |
Line 285... | Line 285... | ||
285 | * @param va Virtual page address. |
285 | * @param va Virtual page address. |
286 | * @param asid Address space identifier. |
286 | * @param asid Address space identifier. |
287 | * @param entry The rest of TLB entry as required by TLB insertion format. |
287 | * @param entry The rest of TLB entry as required by TLB insertion format. |
288 | * @param tr Translation register. |
288 | * @param tr Translation register. |
289 | */ |
289 | */ |
290 | void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr) |
290 | void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
291 | { |
291 | { |
292 | tr_mapping_insert(va, asid, entry, true, tr); |
292 | tr_mapping_insert(va, asid, entry, true, tr); |
293 | } |
293 | } |
294 | 294 | ||
295 | /** Insert data into instruction or data translation register. |
295 | /** Insert data into instruction or data translation register. |
Line 298... | Line 298... | ||
298 | * @param asid Address space identifier. |
298 | * @param asid Address space identifier. |
299 | * @param entry The rest of TLB entry as required by TLB insertion format. |
299 | * @param entry The rest of TLB entry as required by TLB insertion format. |
300 | * @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
300 | * @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
301 | * @param tr Translation register. |
301 | * @param tr Translation register. |
302 | */ |
302 | */ |
303 | void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
303 | void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
304 | { |
304 | { |
305 | region_register rr; |
305 | region_register rr; |
306 | bool restore_rr = false; |
306 | bool restore_rr = false; |
307 | 307 | ||
308 | rr.word = rr_read(VA2VRN(va)); |
308 | rr.word = rr_read(VA2VRN(va)); |
Line 349... | Line 349... | ||
349 | * @param page Virtual page address including VRN bits. |
349 | * @param page Virtual page address including VRN bits. |
350 | * @param frame Physical frame address. |
350 | * @param frame Physical frame address. |
351 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
351 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
352 | * @param tr Translation register if dtr is true, ignored otherwise. |
352 | * @param tr Translation register if dtr is true, ignored otherwise. |
353 | */ |
353 | */ |
354 | void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr) |
354 | void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr) |
355 | { |
355 | { |
356 | tlb_entry_t entry; |
356 | tlb_entry_t entry; |
357 | 357 | ||
358 | entry.word[0] = 0; |
358 | entry.word[0] = 0; |
359 | entry.word[1] = 0; |
359 | entry.word[1] = 0; |
Line 378... | Line 378... | ||
378 | * Purge DTR entries used by the kernel. |
378 | * Purge DTR entries used by the kernel. |
379 | * |
379 | * |
380 | * @param page Virtual page address including VRN bits. |
380 | * @param page Virtual page address including VRN bits. |
381 | * @param width Width of the purge in bits. |
381 | * @param width Width of the purge in bits. |
382 | */ |
382 | */ |
383 | void dtr_purge(__address page, count_t width) |
383 | void dtr_purge(uintptr_t page, count_t width) |
384 | { |
384 | { |
385 | __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
385 | __asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
386 | } |
386 | } |
387 | 387 | ||
388 | 388 | ||
Line 442... | Line 442... | ||
442 | /** Instruction TLB fault handler for faults with VHPT turned off. |
442 | /** Instruction TLB fault handler for faults with VHPT turned off. |
443 | * |
443 | * |
444 | * @param vector Interruption vector. |
444 | * @param vector Interruption vector. |
445 | * @param istate Structure with saved interruption state. |
445 | * @param istate Structure with saved interruption state. |
446 | */ |
446 | */ |
447 | void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate) |
447 | void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) |
448 | { |
448 | { |
449 | region_register rr; |
449 | region_register rr; |
450 | rid_t rid; |
450 | rid_t rid; |
451 | __address va; |
451 | uintptr_t va; |
452 | pte_t *t; |
452 | pte_t *t; |
453 | 453 | ||
454 | va = istate->cr_ifa; /* faulting address */ |
454 | va = istate->cr_ifa; /* faulting address */ |
455 | rr.word = rr_read(VA2VRN(va)); |
455 | rr.word = rr_read(VA2VRN(va)); |
456 | rid = rr.map.rid; |
456 | rid = rr.map.rid; |
Line 479... | Line 479... | ||
479 | /** Data TLB fault handler for faults with VHPT turned off. |
479 | /** Data TLB fault handler for faults with VHPT turned off. |
480 | * |
480 | * |
481 | * @param vector Interruption vector. |
481 | * @param vector Interruption vector. |
482 | * @param istate Structure with saved interruption state. |
482 | * @param istate Structure with saved interruption state. |
483 | */ |
483 | */ |
484 | void alternate_data_tlb_fault(__u64 vector, istate_t *istate) |
484 | void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) |
485 | { |
485 | { |
486 | region_register rr; |
486 | region_register rr; |
487 | rid_t rid; |
487 | rid_t rid; |
488 | __address va; |
488 | uintptr_t va; |
489 | pte_t *t; |
489 | pte_t *t; |
490 | 490 | ||
491 | va = istate->cr_ifa; /* faulting address */ |
491 | va = istate->cr_ifa; /* faulting address */ |
492 | rr.word = rr_read(VA2VRN(va)); |
492 | rr.word = rr_read(VA2VRN(va)); |
493 | rid = rr.map.rid; |
493 | rid = rr.map.rid; |
Line 528... | Line 528... | ||
528 | * This fault should not occur. |
528 | * This fault should not occur. |
529 | * |
529 | * |
530 | * @param vector Interruption vector. |
530 | * @param vector Interruption vector. |
531 | * @param istate Structure with saved interruption state. |
531 | * @param istate Structure with saved interruption state. |
532 | */ |
532 | */ |
533 | void data_nested_tlb_fault(__u64 vector, istate_t *istate) |
533 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
534 | { |
534 | { |
535 | panic("%s\n", __FUNCTION__); |
535 | panic("%s\n", __FUNCTION__); |
536 | } |
536 | } |
537 | 537 | ||
538 | /** Data Dirty bit fault handler. |
538 | /** Data Dirty bit fault handler. |
539 | * |
539 | * |
540 | * @param vector Interruption vector. |
540 | * @param vector Interruption vector. |
541 | * @param istate Structure with saved interruption state. |
541 | * @param istate Structure with saved interruption state. |
542 | */ |
542 | */ |
543 | void data_dirty_bit_fault(__u64 vector, istate_t *istate) |
543 | void data_dirty_bit_fault(uint64_t vector, istate_t *istate) |
544 | { |
544 | { |
545 | region_register rr; |
545 | region_register rr; |
546 | rid_t rid; |
546 | rid_t rid; |
547 | __address va; |
547 | uintptr_t va; |
548 | pte_t *t; |
548 | pte_t *t; |
549 | 549 | ||
550 | va = istate->cr_ifa; /* faulting address */ |
550 | va = istate->cr_ifa; /* faulting address */ |
551 | rr.word = rr_read(VA2VRN(va)); |
551 | rr.word = rr_read(VA2VRN(va)); |
552 | rid = rr.map.rid; |
552 | rid = rr.map.rid; |
Line 575... | Line 575... | ||
575 | /** Instruction access bit fault handler. |
575 | /** Instruction access bit fault handler. |
576 | * |
576 | * |
577 | * @param vector Interruption vector. |
577 | * @param vector Interruption vector. |
578 | * @param istate Structure with saved interruption state. |
578 | * @param istate Structure with saved interruption state. |
579 | */ |
579 | */ |
580 | void instruction_access_bit_fault(__u64 vector, istate_t *istate) |
580 | void instruction_access_bit_fault(uint64_t vector, istate_t *istate) |
581 | { |
581 | { |
582 | region_register rr; |
582 | region_register rr; |
583 | rid_t rid; |
583 | rid_t rid; |
584 | __address va; |
584 | uintptr_t va; |
585 | pte_t *t; |
585 | pte_t *t; |
586 | 586 | ||
587 | va = istate->cr_ifa; /* faulting address */ |
587 | va = istate->cr_ifa; /* faulting address */ |
588 | rr.word = rr_read(VA2VRN(va)); |
588 | rr.word = rr_read(VA2VRN(va)); |
589 | rid = rr.map.rid; |
589 | rid = rr.map.rid; |
Line 612... | Line 612... | ||
612 | /** Data access bit fault handler. |
612 | /** Data access bit fault handler. |
613 | * |
613 | * |
614 | * @param vector Interruption vector. |
614 | * @param vector Interruption vector. |
615 | * @param istate Structure with saved interruption state. |
615 | * @param istate Structure with saved interruption state. |
616 | */ |
616 | */ |
617 | void data_access_bit_fault(__u64 vector, istate_t *istate) |
617 | void data_access_bit_fault(uint64_t vector, istate_t *istate) |
618 | { |
618 | { |
619 | region_register rr; |
619 | region_register rr; |
620 | rid_t rid; |
620 | rid_t rid; |
621 | __address va; |
621 | uintptr_t va; |
622 | pte_t *t; |
622 | pte_t *t; |
623 | 623 | ||
624 | va = istate->cr_ifa; /* faulting address */ |
624 | va = istate->cr_ifa; /* faulting address */ |
625 | rr.word = rr_read(VA2VRN(va)); |
625 | rr.word = rr_read(VA2VRN(va)); |
626 | rid = rr.map.rid; |
626 | rid = rr.map.rid; |
Line 649... | Line 649... | ||
649 | /** Page not present fault handler. |
649 | /** Page not present fault handler. |
650 | * |
650 | * |
651 | * @param vector Interruption vector. |
651 | * @param vector Interruption vector. |
652 | * @param istate Structure with saved interruption state. |
652 | * @param istate Structure with saved interruption state. |
653 | */ |
653 | */ |
654 | void page_not_present(__u64 vector, istate_t *istate) |
654 | void page_not_present(uint64_t vector, istate_t *istate) |
655 | { |
655 | { |
656 | region_register rr; |
656 | region_register rr; |
657 | rid_t rid; |
657 | rid_t rid; |
658 | __address va; |
658 | uintptr_t va; |
659 | pte_t *t; |
659 | pte_t *t; |
660 | 660 | ||
661 | va = istate->cr_ifa; /* faulting address */ |
661 | va = istate->cr_ifa; /* faulting address */ |
662 | rr.word = rr_read(VA2VRN(va)); |
662 | rr.word = rr_read(VA2VRN(va)); |
663 | rid = rr.map.rid; |
663 | rid = rr.map.rid; |