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44 | * This goal is achieved by using procedure calls after RSE becomes operational. |
44 | * This goal is achieved by using procedure calls after RSE becomes operational. |
45 | * |
45 | * |
46 | * Some steps are skipped (enabling and disabling interrupts). |
46 | * Some steps are skipped (enabling and disabling interrupts). |
47 | * Some steps are not fully supported yet (e.g. interruptions |
47 | * Some steps are not fully supported yet (e.g. interruptions |
48 | * from userspace and floating-point context). |
48 | * from userspace and floating-point context). |
- | 49 | * |
|
- | 50 | * @param offs Offset from the beginning of IVT. |
|
- | 51 | * @param handler Interrupt handler address. |
|
49 | */ |
52 | */ |
50 | .macro HEAVYWEIGHT_HANDLER offs handler |
53 | .macro HEAVYWEIGHT_HANDLER offs handler |
51 | .org IVT + \offs |
54 | .org IVT + \offs |
52 | 55 | ||
53 | /* 1. copy interrupt registers into bank 0 */ |
56 | /* 1. copy interrupt registers into bank 0 */ |
Line 98... | Line 101... | ||
98 | 101 | ||
99 | mov r29 = ar.bsp |
102 | mov r29 = ar.bsp |
100 | 103 | ||
101 | st8 [r31] = r27, -8 /* save ar.rnat */ |
104 | st8 [r31] = r27, -8 /* save ar.rnat */ |
102 | st8 [r31] = r28, -8 /* save ar.bspstore */ |
105 | st8 [r31] = r28, -8 /* save ar.bspstore */ |
103 | st8 [r31] = r29 /* save ar.bsp */ |
106 | st8 [r31] = r29, -8 /* save ar.bsp */ |
104 | 107 | ||
105 | mov ar.rsc = r24 /* restore RSE's setting */ |
108 | mov ar.rsc = r24 /* restore RSE's setting */ |
106 | .explicit |
109 | .explicit |
107 | 110 | ||
108 | /* the rest of the save-handler can be kept outside IVT */ |
111 | /* the rest of the save-handler can be kept outside IVT */ |
Line 253... | Line 256... | ||
253 | br.ret.sptk.many rp |
256 | br.ret.sptk.many rp |
254 | 257 | ||
255 | .global heavyweight_handler_finalize |
258 | .global heavyweight_handler_finalize |
256 | heavyweight_handler_finalize: |
259 | heavyweight_handler_finalize: |
257 | /* 16. RSE switch to interrupted context */ |
260 | /* 16. RSE switch to interrupted context */ |
258 | - | ||
259 | /********************************************************************************************/ |
- | |
260 | - | ||
261 | - | ||
262 | - | ||
263 | .auto |
261 | .auto |
264 | cover /*Allocate zerro size frame (Step 1(from Intel Docs))*/ |
262 | cover /* allocate zerro size frame (step 1 (from Intel Docs)) */ |
265 | 263 | ||
266 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 |
264 | add r31 = STACK_SCRATCH_AREA_SIZE, r12 |
267 | 265 | ||
268 | mov r28 = ar.bspstore /*Calculate loadrs (step 2)*/ |
266 | mov r28 = ar.bspstore /* calculate loadrs (step 2) */ |
269 | ld8 r29 = [r31], +8 |
267 | ld8 r29 = [r31], +8 /* load ar.bsp */ |
270 | sub r27 = r29 , r28 |
268 | sub r27 = r29 , r28 |
271 | shl r27 = r27, 16 |
269 | shl r27 = r27, 16 |
272 | 270 | ||
273 | mov r24 = ar.rsc |
271 | mov r24 = ar.rsc |
274 | and r30 = ~3, r24 |
272 | and r30 = ~3, r24 |
275 | or r24 = r30 , r27 |
273 | or r24 = r30 , r27 |
276 | mov ar.rsc = r24 /* place RSE in enforced lazy mode */ |
274 | mov ar.rsc = r24 /* place RSE in enforced lazy mode */ |
277 | 275 | ||
- | 276 | loadrs /* (step 3) */ |
|
278 | 277 | ||
- | 278 | ld8 r28 = [r31], +8 /* load ar.bspstore */ |
|
- | 279 | ld8 r27 = [r31], +8 /* load ar.rnat */ |
|
- | 280 | ld8 r26 = [r31], +8 /* load cr.ifs */ |
|
- | 281 | ld8 r25 = [r31], +8 /* load ar.pfs */ |
|
- | 282 | ld8 r24 = [r31], +8 /* load ar.rsc */ |
|
279 | 283 | ||
- | 284 | mov ar.bspstore = r28 /* (step 4) */ |
|
280 | loadrs /*(Step 3)*/ |
285 | mov ar.rnat = r27 /* (step 5) */ |
281 | - | ||
282 | 286 | ||
283 | /*Read saved registers*/ |
- | |
284 | ld8 r28 = [r31], +8 /*ar.bspstore*/ |
- | |
285 | ld8 r27 = [r31], +8 /*ar.rnat*/ |
- | |
286 | ld8 r26 = [r31], +8 /*cr.ifs*/ |
- | |
287 | ld8 r25 = [r31], +8 /*ar.pfs*/ |
- | |
288 | ld8 r24 = [r31], +8 /*ar.rsc*/ |
- | |
289 | - | ||
290 | - | ||
291 | mov ar.bspstore = r28 /*(Step 4)*/ |
- | |
292 | mov ar.rnat = r27 /*(Step 5)*/ |
- | |
293 | - | ||
294 | mov ar.pfs = r25 /*(Step 6)*/ |
287 | mov ar.pfs = r25 /* (step 6) */ |
295 | mov cr.ifs = r26 |
288 | mov cr.ifs = r26 |
296 | 289 | ||
297 | mov ar.rsc = r24 /*(Step 7)*/ |
290 | mov ar.rsc = r24 /* (step 7) */ |
298 | - | ||
299 | - | ||
300 | .explicit |
291 | .explicit |
301 | 292 | ||
302 | - | ||
303 | /********************************************************************************************/ |
- | |
304 | - | ||
305 | - | ||
306 | - | ||
307 | /* 17. restore interruption state from memory stack */ |
293 | /* 17. restore interruption state from memory stack */ |
308 | - | ||
309 | ld8 r28 = [r31] , +8 ;; /* load cr.ifa */ |
294 | ld8 r28 = [r31], +8 ;; /* load cr.ifa */ |
310 | ld8 r27 = [r31] , +8 ;; /* load cr.isr */ |
295 | ld8 r27 = [r31], +8 ;; /* load cr.isr */ |
311 | ld8 r26 = [r31] , +8 ;; /* load cr.iipa */ |
296 | ld8 r26 = [r31], +8 ;; /* load cr.iipa */ |
312 | ld8 r25 = [r31] , +8 ;; /* load cr.ipsr */ |
297 | ld8 r25 = [r31], +8 ;; /* load cr.ipsr */ |
313 | ld8 r24 = [r31] , +8 ;; /* load cr.iip */ |
298 | ld8 r24 = [r31], +8 ;; /* load cr.iip */ |
314 | 299 | ||
315 | - | ||
316 | mov cr.iip = r24 |
300 | mov cr.iip = r24 |
317 | mov cr.ipsr = r25 |
301 | mov cr.ipsr = r25 |
318 | mov cr.iipa = r26 |
302 | mov cr.iipa = r26 |
319 | mov cr.isr = r27 |
303 | mov cr.isr = r27 |
320 | mov cr.ifa = r28 |
304 | mov cr.ifa = r28 |
321 | 305 | ||
322 | - | ||
323 | - | ||
324 | /* 18. restore predicate registers from memory stack */ |
306 | /* 18. restore predicate registers from memory stack */ |
325 | - | ||
326 | - | ||
327 | ld8 r29 = [r31] , -8 ;; /* load predicate registers */ |
307 | ld8 r29 = [r31] , -8 ;; /* load predicate registers */ |
328 | mov pr =r29 ;; |
308 | mov pr = r29 |
329 | - | ||
330 | add r12 = STACK_FRAME_SIZE,r12;; |
- | |
331 | 309 | ||
332 | /* 19. return from interruption */ |
310 | /* 19. return from interruption */ |
- | 311 | add r12 = STACK_FRAME_SIZE, r12 |
|
333 | rfi;; |
312 | rfi ;; |
334 | 313 | ||
335 | - | ||
336 | dump_gregs: |
314 | dump_gregs: |
337 | mov r16 = REG_DUMP;; |
315 | mov r16 = REG_DUMP;; |
338 | st8 [r16] = r0;; |
316 | st8 [r16] = r0;; |
339 | add r16 = 8,r16 ;; |
317 | add r16 = 8,r16 ;; |
340 | st8 [r16] = r1;; |
318 | st8 [r16] = r1;; |