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134 | 134 | ||
135 | #include <arch/types.h> |
135 | #include <arch/types.h> |
136 | 136 | ||
137 | /** Processor Status Register. */ |
137 | /** Processor Status Register. */ |
138 | union psr { |
138 | union psr { |
139 | __u64 value; |
139 | uint64_t value; |
140 | struct { |
140 | struct { |
141 | unsigned : 1; |
141 | unsigned : 1; |
142 | unsigned be : 1; /**< Big-Endian data accesses. */ |
142 | unsigned be : 1; /**< Big-Endian data accesses. */ |
143 | unsigned up : 1; /**< User Performance monitor enable. */ |
143 | unsigned up : 1; /**< User Performance monitor enable. */ |
144 | unsigned ac : 1; /**< Alignment Check. */ |
144 | unsigned ac : 1; /**< Alignment Check. */ |
Line 177... | Line 177... | ||
177 | }; |
177 | }; |
178 | typedef union psr psr_t; |
178 | typedef union psr psr_t; |
179 | 179 | ||
180 | /** Register Stack Configuration Register */ |
180 | /** Register Stack Configuration Register */ |
181 | union rsc { |
181 | union rsc { |
182 | __u64 value; |
182 | uint64_t value; |
183 | struct { |
183 | struct { |
184 | unsigned mode : 2; |
184 | unsigned mode : 2; |
185 | unsigned pl : 2; /**< Privilege Level. */ |
185 | unsigned pl : 2; /**< Privilege Level. */ |
186 | unsigned be : 1; /**< Big-endian. */ |
186 | unsigned be : 1; /**< Big-endian. */ |
187 | unsigned : 11; |
187 | unsigned : 11; |
Line 190... | Line 190... | ||
190 | }; |
190 | }; |
191 | typedef union rsc rsc_t; |
191 | typedef union rsc rsc_t; |
192 | 192 | ||
193 | /** External Interrupt Vector Register */ |
193 | /** External Interrupt Vector Register */ |
194 | union cr_ivr { |
194 | union cr_ivr { |
195 | __u8 vector; |
195 | uint8_t vector; |
196 | __u64 value; |
196 | uint64_t value; |
197 | }; |
197 | }; |
198 | 198 | ||
199 | typedef union cr_ivr cr_ivr_t; |
199 | typedef union cr_ivr cr_ivr_t; |
200 | 200 | ||
201 | /** Task Priority Register */ |
201 | /** Task Priority Register */ |
Line 204... | Line 204... | ||
204 | unsigned : 4; |
204 | unsigned : 4; |
205 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
205 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
206 | unsigned : 8; |
206 | unsigned : 8; |
207 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
207 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
208 | } __attribute__ ((packed)); |
208 | } __attribute__ ((packed)); |
209 | __u64 value; |
209 | uint64_t value; |
210 | }; |
210 | }; |
211 | 211 | ||
212 | typedef union cr_tpr cr_tpr_t; |
212 | typedef union cr_tpr cr_tpr_t; |
213 | 213 | ||
214 | /** Interval Timer Vector */ |
214 | /** Interval Timer Vector */ |
Line 218... | Line 218... | ||
218 | unsigned : 4; |
218 | unsigned : 4; |
219 | unsigned : 1; |
219 | unsigned : 1; |
220 | unsigned : 3; |
220 | unsigned : 3; |
221 | unsigned m : 1; /**< Mask. */ |
221 | unsigned m : 1; /**< Mask. */ |
222 | } __attribute__ ((packed)); |
222 | } __attribute__ ((packed)); |
223 | __u64 value; |
223 | uint64_t value; |
224 | }; |
224 | }; |
225 | 225 | ||
226 | typedef union cr_itv cr_itv_t; |
226 | typedef union cr_itv cr_itv_t; |
227 | 227 | ||
228 | /** Interruption Status Register */ |
228 | /** Interruption Status Register */ |
Line 232... | Line 232... | ||
232 | /** General Exception code field structuring. */ |
232 | /** General Exception code field structuring. */ |
233 | struct { |
233 | struct { |
234 | unsigned ge_na : 4; |
234 | unsigned ge_na : 4; |
235 | unsigned ge_code : 4; |
235 | unsigned ge_code : 4; |
236 | } __attribute__ ((packed)); |
236 | } __attribute__ ((packed)); |
237 | __u16 code; |
237 | uint16_t code; |
238 | }; |
238 | }; |
239 | __u8 vector; |
239 | uint8_t vector; |
240 | unsigned : 8; |
240 | unsigned : 8; |
241 | unsigned x : 1; /**< Execute exception. */ |
241 | unsigned x : 1; /**< Execute exception. */ |
242 | unsigned w : 1; /**< Write exception. */ |
242 | unsigned w : 1; /**< Write exception. */ |
243 | unsigned r : 1; /**< Read exception. */ |
243 | unsigned r : 1; /**< Read exception. */ |
244 | unsigned na : 1; /**< Non-access exception. */ |
244 | unsigned na : 1; /**< Non-access exception. */ |
Line 249... | Line 249... | ||
249 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
249 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
250 | unsigned ei : 2; /**< Excepting Instruction. */ |
250 | unsigned ei : 2; /**< Excepting Instruction. */ |
251 | unsigned ed : 1; /**< Exception Deferral. */ |
251 | unsigned ed : 1; /**< Exception Deferral. */ |
252 | unsigned : 20; |
252 | unsigned : 20; |
253 | } __attribute__ ((packed)); |
253 | } __attribute__ ((packed)); |
254 | __u64 value; |
254 | uint64_t value; |
255 | }; |
255 | }; |
256 | 256 | ||
257 | typedef union cr_isr cr_isr_t; |
257 | typedef union cr_isr cr_isr_t; |
258 | 258 | ||
259 | /** CPUID Register 3 */ |
259 | /** CPUID Register 3 */ |
260 | union cpuid3 { |
260 | union cpuid3 { |
261 | struct { |
261 | struct { |
262 | __u8 number; |
262 | uint8_t number; |
263 | __u8 revision; |
263 | uint8_t revision; |
264 | __u8 model; |
264 | uint8_t model; |
265 | __u8 family; |
265 | uint8_t family; |
266 | __u8 archrev; |
266 | uint8_t archrev; |
267 | } __attribute__ ((packed)); |
267 | } __attribute__ ((packed)); |
268 | __u64 value; |
268 | uint64_t value; |
269 | }; |
269 | }; |
270 | 270 | ||
271 | typedef union cpuid3 cpuid3_t; |
271 | typedef union cpuid3 cpuid3_t; |
272 | 272 | ||
273 | #endif /* !__ASM__ */ |
273 | #endif /* !__ASM__ */ |