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Line 80... | Line 80... | ||
80 | return v; |
80 | return v; |
81 | } |
81 | } |
82 | 82 | ||
83 | /** Write IVA (Interruption Vector Address) register. |
83 | /** Write IVA (Interruption Vector Address) register. |
84 | * |
84 | * |
85 | * @param New location of interruption vector table. |
85 | * @param v New location of interruption vector table. |
86 | */ |
86 | */ |
87 | static inline void iva_write(__u64 v) |
87 | static inline void iva_write(__u64 v) |
88 | { |
88 | { |
89 | __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); |
89 | __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); |
90 | } |
90 | } |
Line 103... | Line 103... | ||
103 | return v; |
103 | return v; |
104 | } |
104 | } |
105 | 105 | ||
106 | /** Write ITC (Interval Timer Counter) register. |
106 | /** Write ITC (Interval Timer Counter) register. |
107 | * |
107 | * |
108 | * @param New counter value. |
108 | * @param v New counter value. |
109 | */ |
109 | */ |
110 | static inline void itc_write(__u64 v) |
110 | static inline void itc_write(__u64 v) |
111 | { |
111 | { |
112 | __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
112 | __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); |
113 | } |
113 | } |
Line 125... | Line 125... | ||
125 | return v; |
125 | return v; |
126 | } |
126 | } |
127 | 127 | ||
128 | /** Write ITM (Interval Timer Match) register. |
128 | /** Write ITM (Interval Timer Match) register. |
129 | * |
129 | * |
130 | * @param New match value. |
130 | * @param v New match value. |
131 | */ |
131 | */ |
132 | static inline void itm_write(__u64 v) |
132 | static inline void itm_write(__u64 v) |
133 | { |
133 | { |
134 | __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
134 | __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); |
135 | } |
135 | } |
Line 160... | Line 160... | ||
160 | return v; |
160 | return v; |
161 | } |
161 | } |
162 | 162 | ||
163 | /** Write ITV (Interval Timer Vector) register. |
163 | /** Write ITV (Interval Timer Vector) register. |
164 | * |
164 | * |
165 | * @param New vector and mask bit. |
165 | * @param v New vector and mask bit. |
166 | */ |
166 | */ |
167 | static inline void itv_write(__u64 v) |
167 | static inline void itv_write(__u64 v) |
168 | { |
168 | { |
169 | __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
169 | __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); |
170 | } |
170 | } |
171 | 171 | ||
172 | /** Write EOI (End Of Interrupt) register. |
172 | /** Write EOI (End Of Interrupt) register. |
173 | * |
173 | * |
174 | * @param This value is ignored. |
174 | * @param v This value is ignored. |
175 | */ |
175 | */ |
176 | static inline void eoi_write(__u64 v) |
176 | static inline void eoi_write(__u64 v) |
177 | { |
177 | { |
178 | __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
178 | __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); |
179 | } |
179 | } |
Line 191... | Line 191... | ||
191 | return v; |
191 | return v; |
192 | } |
192 | } |
193 | 193 | ||
194 | /** Write TPR (Task Priority Register). |
194 | /** Write TPR (Task Priority Register). |
195 | * |
195 | * |
196 | * @param New value of TPR. |
196 | * @param v New value of TPR. |
197 | */ |
197 | */ |
198 | static inline void tpr_write(__u64 v) |
198 | static inline void tpr_write(__u64 v) |
199 | { |
199 | { |
200 | __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
200 | __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); |
201 | } |
201 | } |