WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/ia32/include/asm.h



 
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
 
extern uint32_t interrupt_handler_size;
 
extern void paging_on(void);
 
extern void interrupt_handlers(void);
 
extern void enable_l_apic_in_msr(void);
 
 
extern void asm_delay_loop(uint32_t t);
extern void asm_fake_loop(uint32_t t);
 
 
/** Halt CPU
 *
 * Halt the current CPU until interrupt event.
 */
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
 
#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
    { \
    unative_t res; \
    __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
    return res; \
    }
 
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
    { \
    __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
    }
 
GEN_READ_REG(cr0);

 * Output byte to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Word to port
 *
 * Output word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Double word to port
 *
 * Output double word to port
 *
 * @param port Port to write to
 * @param val Value to write
 */
static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
 
/** Byte from port
 *
 * Get byte from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Word from port
 *
 * Get word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Double word from port
 *
 * Get double word from port
 *
 * @param port Port to read from
 * @return Value read
 */
static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EFLAGS.

 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
   
    return v;
}
 
static inline uint64_t rdtsc(void)
{
    uint64_t v;
   
    __asm__ volatile("rdtsc\n" : "=A" (v));
   
    return v;
}
 
/** Return current IP address */
static inline uintptr_t * get_ip()
{
    uintptr_t *ip;
 
    __asm__ volatile (
        "mov %%eip, %0"
        : "=r" (ip)
        );

 
/** Invalidate TLB Entry.
 *
 * @param addr Address on a page whose TLB entry is to be invalidated.
 */
static inline void invlpg(uintptr_t addr)
{
    __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
}
 
/** Load GDTR register from memory.
 *
 * @param gdtr_reg Address of memory from where to load GDTR.

 
/** Load TR from descriptor table.
 *
 * @param sel Selector specifying descriptor of TSS segment.
 */
static inline void tr_load(uint16_t sel)
{
    __asm__ volatile ("ltr %0" : : "r" (sel));
}
 
#endif

Rev 1702	Rev 1780
Line 38...	Line 38...
38		38
39	#include <arch/pm.h>	39	#include <arch/pm.h>
40	#include <arch/types.h>	40	#include <arch/types.h>
41	#include <config.h>	41	#include <config.h>
42		42
43	extern __u32 interrupt_handler_size;	43	extern uint32_t interrupt_handler_size;
44		44
45	extern void paging_on(void);	45	extern void paging_on(void);
46		46
47	extern void interrupt_handlers(void);	47	extern void interrupt_handlers(void);
48		48
49	extern void enable_l_apic_in_msr(void);	49	extern void enable_l_apic_in_msr(void);
50		50
51		51
52	extern void asm_delay_loop(__u32 t);	52	extern void asm_delay_loop(uint32_t t);
53	extern void asm_fake_loop(__u32 t);	53	extern void asm_fake_loop(uint32_t t);
54		54
55		55
56	/** Halt CPU	56	/** Halt CPU
57	*	57	*
58	* Halt the current CPU until interrupt event.	58	* Halt the current CPU until interrupt event.
59	*/	59	*/
60	static inline void cpu_halt(void) { __asm__("hlt\n"); };	60	static inline void cpu_halt(void) { __asm__("hlt\n"); };
61	static inline void cpu_sleep(void) { __asm__("hlt\n"); };	61	static inline void cpu_sleep(void) { __asm__("hlt\n"); };
62		62
63	#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \	63	#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
64	{ \	64	{ \
65	__native res; \	65	unative_t res; \
66	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \	66	__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
67	return res; \	67	return res; \
68	}	68	}
69		69
70	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \	70	#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
71	{ \	71	{ \
72	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \	72	__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
73	}	73	}
74		74
75	GEN_READ_REG(cr0);	75	GEN_READ_REG(cr0);
Line 96...	Line 96...
96	* Output byte to port	96	* Output byte to port
97	*	97	*
98	* @param port Port to write to	98	* @param port Port to write to
99	* @param val Value to write	99	* @param val Value to write
100	*/	100	*/
101	static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }	101	static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
102		102
103	/** Word to port	103	/** Word to port
104	*	104	*
105	* Output word to port	105	* Output word to port
106	*	106	*
107	* @param port Port to write to	107	* @param port Port to write to
108	* @param val Value to write	108	* @param val Value to write
109	*/	109	*/
110	static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }	110	static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
111		111
112	/** Double word to port	112	/** Double word to port
113	*	113	*
114	* Output double word to port	114	* Output double word to port
115	*	115	*
116	* @param port Port to write to	116	* @param port Port to write to
117	* @param val Value to write	117	* @param val Value to write
118	*/	118	*/
119	static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }	119	static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
120		120
121	/** Byte from port	121	/** Byte from port
122	*	122	*
123	* Get byte from port	123	* Get byte from port
124	*	124	*
125	* @param port Port to read from	125	* @param port Port to read from
126	* @return Value read	126	* @return Value read
127	*/	127	*/
128	static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }	128	static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
129		129
130	/** Word from port	130	/** Word from port
131	*	131	*
132	* Get word from port	132	* Get word from port
133	*	133	*
134	* @param port Port to read from	134	* @param port Port to read from
135	* @return Value read	135	* @return Value read
136	*/	136	*/
137	static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }	137	static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
138		138
139	/** Double word from port	139	/** Double word from port
140	*	140	*
141	* Get double word from port	141	* Get double word from port
142	*	142	*
143	* @param port Port to read from	143	* @param port Port to read from
144	* @return Value read	144	* @return Value read
145	*/	145	*/
146	static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }	146	static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
147		147
148	/** Enable interrupts.	148	/** Enable interrupts.
149	*	149	*
150	* Enable interrupts and return previous	150	* Enable interrupts and return previous
151	* value of EFLAGS.	151	* value of EFLAGS.
Line 217...	Line 217...
217	*	217	*
218	* Return the base address of the current stack.	218	* Return the base address of the current stack.
219	* The stack is assumed to be STACK_SIZE bytes long.	219	* The stack is assumed to be STACK_SIZE bytes long.
220	* The stack must start on page boundary.	220	* The stack must start on page boundary.
221	*/	221	*/
222	static inline __address get_stack_base(void)	222	static inline uintptr_t get_stack_base(void)
223	{	223	{
224	__address v;	224	uintptr_t v;
225		225
226	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));	226	__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
227		227
228	return v;	228	return v;
229	}	229	}
230		230
231	static inline __u64 rdtsc(void)	231	static inline uint64_t rdtsc(void)
232	{	232	{
233	__u64 v;	233	uint64_t v;
234		234
235	__asm__ volatile("rdtsc\n" : "=A" (v));	235	__asm__ volatile("rdtsc\n" : "=A" (v));
236		236
237	return v;	237	return v;
238	}	238	}
239		239
240	/** Return current IP address */	240	/** Return current IP address */
241	static inline __address * get_ip()	241	static inline uintptr_t * get_ip()
242	{	242	{
243	__address *ip;	243	uintptr_t *ip;
244		244
245	__asm__ volatile (	245	__asm__ volatile (
246	"mov %%eip, %0"	246	"mov %%eip, %0"
247	: "=r" (ip)	247	: "=r" (ip)
248	);	248	);
Line 251...	Line 251...
251		251
252	/** Invalidate TLB Entry.	252	/** Invalidate TLB Entry.
253	*	253	*
254	* @param addr Address on a page whose TLB entry is to be invalidated.	254	* @param addr Address on a page whose TLB entry is to be invalidated.
255	*/	255	*/
256	static inline void invlpg(__address addr)	256	static inline void invlpg(uintptr_t addr)
257	{	257	{
258	__asm__ volatile ("invlpg %0\n" :: "m" ((__native )addr));	258	__asm__ volatile ("invlpg %0\n" :: "m" ((unative_t )addr));
259	}	259	}
260		260
261	/** Load GDTR register from memory.	261	/** Load GDTR register from memory.
262	*	262	*
263	* @param gdtr_reg Address of memory from where to load GDTR.	263	* @param gdtr_reg Address of memory from where to load GDTR.
Line 287...	Line 287...
287		287
288	/** Load TR from descriptor table.	288	/** Load TR from descriptor table.
289	*	289	*
290	* @param sel Selector specifying descriptor of TSS segment.	290	* @param sel Selector specifying descriptor of TSS segment.
291	*/	291	*/
292	static inline void tr_load(__u16 sel)	292	static inline void tr_load(uint16_t sel)
293	{	293	{
294	__asm__ volatile ("ltr %0" : : "r" (sel));	294	__asm__ volatile ("ltr %0" : : "r" (sel));
295	}	295	}
296		296
297	#endif	297	#endif

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(root)/kernel/trunk/arch/ia32/include/asm.h @ 1223 – Rev 1702 → 1780