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        TLB according to messages found in its TLB shootdown message queue. In
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        TLB according to messages found in its TLB shootdown message queue. In
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        the end, each processor sets its TLB flag and resumes its previous
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        the end, each processor sets its TLB flag and resumes its previous
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        operation.</para>
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        operation.</para>
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      </formalpara>
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      </formalpara>
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    </section>
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    </section>
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  </section>
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    <section>
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  <section>
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      <title>Address spaces</title>
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    <title>Address spaces</title>
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      <section>
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        <indexterm>
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          <primary>address space</primary>
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    <para>last bits about address spaces</para>
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          <secondary>- area</secondary>
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        </indexterm>
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        <title>Address space areas</title>
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        <para>Each address space consists of mutually disjunctive continuous
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        address space areas. Address space area is precisely defined by its
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        base address and the number of frames/pages is contains.</para>
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        <para>Address space area , that define behaviour and permissions on
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        the particular area. <itemizedlist>
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            <listitem><emphasis>AS_AREA_READ</emphasis> flag indicates reading
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            permission.</listitem>
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            <listitem><emphasis>AS_AREA_WRITE</emphasis> flag indicates
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            writing permission.</listitem>
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            <listitem><emphasis>AS_AREA_EXEC</emphasis> flag indicates code
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            execution permission. Some architectures do not support execution
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            persmission restriction. In this case this flag has no
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            effect.</listitem>
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            <listitem><emphasis>AS_AREA_DEVICE</emphasis> marks area as mapped
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            to the device memory.</listitem>
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          </itemizedlist></para>
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        <para>Kernel provides possibility tasks create/expand/shrink/share its
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        address space via the set of syscalls.</para>
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      </section>
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      <section>
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    <section>
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        <indexterm>
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      <indexterm>
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          <primary>address space</primary>
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        <primary>address space</primary>
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          <secondary>- ASID</secondary>
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        <secondary>- ASID</secondary>
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        </indexterm>
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      </indexterm>
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        <title>Address Space ID (ASID)</title>
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      <title>Address Space ID (ASID)</title>
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        <para>Every task in the operating system has it's own view of the
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      <para>Modern processor architectures optimize TLB utilization by
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        virtual memory. When performing context switch between different
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      associating TLB entries with address spaces through assigning
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        tasks, the kernel must switch the address space mapping as well. As
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      identification numbers to them. In HelenOS, the term ASID, originally
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        modern processors perform very aggressive caching of virtual mappings,
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      taken from the mips32 terminology, is used to refer to the address space
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        flushing the complete TLB on every context switch would be very
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      identification number. The advantage of having ASIDs is that TLB does
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        inefficient. To avoid such performance penalty, some architectures
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      not have to be invalidated on thread context switch as long as ASIDs are
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        introduce an address space identifier, which allows storing several
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      unique. Unfotunatelly, architectures supported by HelenOS use all
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        different mappings inside TLB.</para>
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      different widths of ASID numbers<footnote>
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        <para>HelenOS kernel can take advantage of this hardware support by
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          <para>amd64 and ia32 don't use similar abstraction at all, mips32
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        having an ASID abstraction. I.e. on ia64 kernel ASID is derived from
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          has 8-bit ASIDs and ia64 can have ASIDs between 18 to 24 bits
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          wide.</para>
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        RID (region identifier) and on the mips32 kernel ASID is actually the
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        </footnote> out of which none is sufficient. The amd64 and ia32
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        hardware identifier. As expected, this ASID information record is the
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      architectures cannot make use of ASIDs as their TLB doesn't recognize
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        part of <emphasis>as_t</emphasis> structure.</para>
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      such an abstraction. Other architectures have support for ASIDs, but for
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        <para>Due to the hardware limitations, hardware ASID has limited
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      instance ppc32 doesn't make use of them in the current version of
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        length from 8 bits on ia64 to 24 bits on mips32, which makes it
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      HelenOS. The rest of the architectures does use ASIDs. However, even on
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      the ia64 architecture, the minimal supported width of ASID<footnote>
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          <para>RID in ia64 terminology.</para>
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        impossible to use it as unique address space identifier for all tasks
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        </footnote> is insufficient to provide a unique integer identifier to
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        running in the system. In such situations special ASID stealing
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      all address spaces that might hypothetically coexist in the running
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        algoritm is used, which takes ASID from inactive task and assigns it
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      system. The situation on mips32 is even worse: the architecture has only
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        to the active task.</para>
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      256 unique identifiers.</para>
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        <indexterm>
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      <indexterm>
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          <primary>address space</primary>
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        <primary>address space</primary>
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          <secondary>- ASID stealing</secondary>
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        <secondary>- ASID stealing</secondary>
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        </indexterm>
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      </indexterm>
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      <para>To mitigate the shortage of ASIDs, HelenOS uses the following
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        <para>
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      strategy. When the system initializes, a FIFO queue<footnote>
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          <classname>ASID stealing algoritm here.</classname>
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          <para>Note that architecture-specific measures are taken to avoid
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          too large FIFO queue. For instance, seven consecutive ia64 RIDs are
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        </para>
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          grouped to form one HelenOS ASID.</para>
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        </footnote> is created and filled with all available ASIDs. Moreover,
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      every address space remembers the number of processors on which it is
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      active. Address spaces that have a valid ASID and that are not active on
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      any processor are appended to the list of inactive address spaces with
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      valid ASID. When an address space needs to be assigned a valid ASID, it
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      first checks the FIFO queue. If it contains at least one ASID, the ASID
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      is allocated. If the queue is empty, an ASID is simply stolen from the
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      first address space in the list. In that case, the address space that
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      loses the ASID in favor of another address space, is removed from the
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      list. After the new ASID is purged from all TLBs, it can be used by the
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      address space. Note that this approach works due to the fact that the
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      number of ASIDs is greater than the maximal number of processors
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      supported by HelenOS and that there can be only one active address space
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      per processor. In other words, when the FIFO queue is empty, there must
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      </section>
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      be address spaces that are not active on any processor.</para>
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    </section>
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    </section>
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  </section>
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  </section>
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</chapter>
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</chapter>
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