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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
- | 29 | #include <arch/stack.h> |
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- | 30 | ||
- | 31 | #define STACK_ITEMS 12 |
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- | 32 | #define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE) |
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- | 33 | ||
- | 34 | #if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0) |
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- | 35 | #error Memory stack must be 16-byte aligned. |
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- | 36 | #endif |
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29 | 37 | ||
30 | /** Heavyweight interrupt handler |
38 | /** Heavyweight interrupt handler |
31 | * |
39 | * |
32 | * This macro roughly follows steps from 1 to 19 described in |
40 | * This macro roughly follows steps from 1 to 19 described in |
33 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
41 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
Line 55... | Line 63... | ||
55 | /* 3. switch to kernel memory stack */ |
63 | /* 3. switch to kernel memory stack */ |
56 | /* TODO: support interruptions from userspace */ |
64 | /* TODO: support interruptions from userspace */ |
57 | /* assume kernel stack */ |
65 | /* assume kernel stack */ |
58 | 66 | ||
59 | /* 4. save registers in bank 0 into memory stack */ |
67 | /* 4. save registers in bank 0 into memory stack */ |
60 | add r12 = -8, r12 ;; |
68 | add r31 = -8, r12 ;; |
- | 69 | add r12 = -STACK_FRAME_SIZE, r12 ;; |
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61 | 70 | ||
62 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
71 | st8 [r31] = r29, -8 ;; /* save predicate registers */ |
63 | 72 | ||
64 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
73 | st8 [r31] = r24, -8 ;; /* save cr.iip */ |
65 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
74 | st8 [r31] = r25, -8 ;; /* save cr.ipsr */ |
66 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
75 | st8 [r31] = r26, -8 ;; /* save cr.iipa */ |
67 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
76 | st8 [r31] = r27, -8 ;; /* save cr.isr */ |
68 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
77 | st8 [r31] = r28, -8 ;; /* save cr.ifa */ |
69 | 78 | ||
70 | /* 5. RSE switch from interrupted context */ |
79 | /* 5. RSE switch from interrupted context */ |
71 | .auto |
80 | .auto |
72 | mov r24 = ar.rsc |
81 | mov r24 = ar.rsc |
73 | mov r25 = ar.pfs |
82 | mov r25 = ar.pfs |
74 | cover |
83 | cover |
75 | mov r26 = cr.ifs |
84 | mov r26 = cr.ifs |
76 | 85 | ||
77 | st8 [r12] = r24, -8 /* save ar.rsc */ |
86 | st8 [r31] = r24, -8 /* save ar.rsc */ |
78 | st8 [r12] = r25, -8 /* save ar.pfs */ |
87 | st8 [r31] = r25, -8 /* save ar.pfs */ |
79 | st8 [r12] = r26, -8 /* save ar.ifs */ |
88 | st8 [r31] = r26, -8 /* save ar.ifs */ |
80 | 89 | ||
81 | and r30 = ~3, r24 |
90 | and r30 = ~3, r24 |
82 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
91 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
83 | 92 | ||
84 | mov r27 = ar.rnat |
93 | mov r27 = ar.rnat |
Line 87... | Line 96... | ||
87 | /* assume kernel backing store */ |
96 | /* assume kernel backing store */ |
88 | mov ar.bspstore = r28 |
97 | mov ar.bspstore = r28 |
89 | 98 | ||
90 | mov r29 = ar.bsp |
99 | mov r29 = ar.bsp |
91 | 100 | ||
92 | st8 [r12] = r27, -8 /* save ar.rnat */ |
101 | st8 [r31] = r27, -8 /* save ar.rnat */ |
93 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
102 | st8 [r31] = r28, -8 /* save ar.bspstore */ |
94 | st8 [r12] = r29 /* save ar.bsp */ |
103 | st8 [r31] = r29 /* save ar.bsp */ |
95 | 104 | ||
96 | mov ar.rsc = r24 /* restore RSE's setting */ |
105 | mov ar.rsc = r24 /* restore RSE's setting */ |
97 | .explicit |
106 | .explicit |
98 | 107 | ||
99 | /* the rest of the save-handler can be kept outside IVT */ |
108 | /* the rest of the save-handler can be kept outside IVT */ |