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Rev 3424 | Rev 4377 | ||
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Line 110... | Line 110... | ||
110 | d->offset_16_31 = offset >> 16; |
110 | d->offset_16_31 = offset >> 16; |
111 | } |
111 | } |
112 | 112 | ||
113 | void tss_initialize(tss_t *t) |
113 | void tss_initialize(tss_t *t) |
114 | { |
114 | { |
115 | memsetb(t, sizeof(struct tss), 0); |
115 | memsetb(t, sizeof(tss_t), 0); |
116 | } |
116 | } |
117 | 117 | ||
118 | /* |
118 | /* |
119 | * This function takes care of proper setup of IDT and IDTR. |
119 | * This function takes care of proper setup of IDT and IDTR. |
120 | */ |
120 | */ |
Line 125... | Line 125... | ||
125 | 125 | ||
126 | for (i = 0; i < IDT_ITEMS; i++) { |
126 | for (i = 0; i < IDT_ITEMS; i++) { |
127 | d = &idt[i]; |
127 | d = &idt[i]; |
128 | 128 | ||
129 | d->unused = 0; |
129 | d->unused = 0; |
130 | d->selector = selector(KTEXT_DES); |
130 | d->selector = gdtselector(KTEXT_DES); |
131 | 131 | ||
132 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
132 | d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */ |
133 | 133 | ||
134 | if (i == VECTOR_SYSCALL || i == VECTOR_BREAKPOINT) { |
134 | if (i == VECTOR_SYSCALL || i == VECTOR_BREAKPOINT) { |
135 | /* |
135 | /* |
Line 196... | Line 196... | ||
196 | tss_p = &tss; |
196 | tss_p = &tss; |
197 | } |
197 | } |
198 | else { |
198 | else { |
199 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
199 | tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC); |
200 | if (!tss_p) |
200 | if (!tss_p) |
201 | panic("could not allocate TSS\n"); |
201 | panic("Cannot allocate TSS."); |
202 | } |
202 | } |
203 | 203 | ||
204 | tss_initialize(tss_p); |
204 | tss_initialize(tss_p); |
205 | 205 | ||
206 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
206 | gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL; |
Line 212... | Line 212... | ||
212 | 212 | ||
213 | /* |
213 | /* |
214 | * As of this moment, the current CPU has its own GDT pointing |
214 | * As of this moment, the current CPU has its own GDT pointing |
215 | * to its own TSS. We just need to load the TR register. |
215 | * to its own TSS. We just need to load the TR register. |
216 | */ |
216 | */ |
217 | tr_load(selector(TSS_DES)); |
217 | tr_load(gdtselector(TSS_DES)); |
218 | 218 | ||
219 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
219 | clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */ |
220 | clean_AM_flag(); /* Disable alignment check */ |
220 | clean_AM_flag(); /* Disable alignment check */ |
221 | } |
221 | } |
222 | 222 | ||
Line 230... | Line 230... | ||
230 | gdt_setbase(&gdt_p[TLS_DES], tls); |
230 | gdt_setbase(&gdt_p[TLS_DES], tls); |
231 | /* Reload gdt register to update GS in CPU */ |
231 | /* Reload gdt register to update GS in CPU */ |
232 | gdtr_load(&cpugdtr); |
232 | gdtr_load(&cpugdtr); |
233 | } |
233 | } |
234 | 234 | ||
235 | /* Reboot the machine by initiating |
- | |
236 | * a triple fault |
- | |
237 | */ |
- | |
238 | void arch_reboot(void) |
- | |
239 | { |
- | |
240 | preemption_disable(); |
- | |
241 | ipl_t ipl = interrupts_disable(); |
- | |
242 | - | ||
243 | memsetb(idt, sizeof(idt), 0); |
- | |
244 | - | ||
245 | ptr_16_32_t idtr; |
- | |
246 | idtr.limit = sizeof(idt); |
- | |
247 | idtr.base = (uintptr_t) idt; |
- | |
248 | idtr_load(&idtr); |
- | |
249 | - | ||
250 | interrupts_restore(ipl); |
- | |
251 | asm volatile ( |
- | |
252 | "int $0x03\n" |
- | |
253 | "cli\n" |
- | |
254 | "hlt\n" |
- | |
255 | ); |
- | |
256 | } |
- | |
257 | - | ||
258 | /** @} |
235 | /** @} |
259 | */ |
236 | */ |