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Rev 3493 | Rev 3591 | ||
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Line 39... | Line 39... | ||
39 | #define ITLB_ENTRY_COUNT 64 |
39 | #define ITLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
40 | #define DTLB_ENTRY_COUNT 64 |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
41 | #define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT |
42 | #endif |
42 | #endif |
43 | 43 | ||
44 | /** DT16 is the only of the three DMMUs that can hold locked entries. */ |
44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
45 | #if defined (US3) |
45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
47 | #endif |
47 | #endif |
48 | 48 | ||
49 | #define MEM_CONTEXT_KERNEL 0 |
49 | #define MEM_CONTEXT_KERNEL 0 |
Line 72... | Line 72... | ||
72 | #define TLB_DEMAP_SECONDARY 1 |
72 | #define TLB_DEMAP_SECONDARY 1 |
73 | #define TLB_DEMAP_NUCLEUS 2 |
73 | #define TLB_DEMAP_NUCLEUS 2 |
74 | 74 | ||
75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
75 | /* There are more TLBs in one MMU in US3, their codes are defined here. */ |
76 | #if defined (US3) |
76 | #if defined (US3) |
77 | /* D-MMU: one 16-entry TLB and two 512-entry TLBs */ |
77 | /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ |
78 | #define TLB_DT16 0 |
78 | #define TLB_DSMALL 0 |
79 | #define TLB_DT512_0 2 |
79 | #define TLB_DBIG_0 2 |
80 | #define TLB_DT512_1 3 |
80 | #define TLB_DBIG_1 3 |
81 | 81 | ||
82 | /* I-MMU: one 16-entry TLB and one 128-entry TLB */ |
82 | /* I-MMU: one small (16-entry) TLB and one big TLB */ |
83 | #define TLB_IT16 0 |
83 | #define TLB_ISMALL 0 |
84 | #define TLB_IT128 2 |
84 | #define TLB_IBIG 2 |
85 | #endif |
85 | #endif |
86 | 86 | ||
87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
87 | #define TLB_DEMAP_CONTEXT_SHIFT 4 |
88 | 88 | ||
89 | /* TLB Tag Access shifts */ |
89 | /* TLB Tag Access shifts */ |
Line 97... | Line 97... | ||
97 | #include <arch/mm/mmu.h> |
97 | #include <arch/mm/mmu.h> |
98 | #include <arch/mm/page.h> |
98 | #include <arch/mm/page.h> |
99 | #include <arch/asm.h> |
99 | #include <arch/asm.h> |
100 | #include <arch/barrier.h> |
100 | #include <arch/barrier.h> |
101 | #include <arch/types.h> |
101 | #include <arch/types.h> |
- | 102 | #include <arch/register.h> |
|
- | 103 | #include <arch/cpu.h> |
|
102 | 104 | ||
103 | union tlb_context_reg { |
105 | union tlb_context_reg { |
104 | uint64_t v; |
106 | uint64_t v; |
105 | struct { |
107 | struct { |
106 | unsigned long : 51; |
108 | unsigned long : 51; |
Line 228... | Line 230... | ||
228 | unsigned fv : 1; /**< Fault Valid bit. */ |
230 | unsigned fv : 1; /**< Fault Valid bit. */ |
229 | } __attribute__ ((packed)); |
231 | } __attribute__ ((packed)); |
230 | }; |
232 | }; |
231 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
233 | typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
232 | 234 | ||
- | 235 | #if defined (US3) |
|
- | 236 | ||
- | 237 | /* |
|
- | 238 | * Functions for determining the number of entries in TLBs. They either return |
|
- | 239 | * a constant value or a value based on the CPU autodetection. |
|
- | 240 | */ |
|
- | 241 | ||
- | 242 | /** |
|
- | 243 | * Determine the number od entries in the DMMU's small TLB. |
|
- | 244 | */ |
|
- | 245 | static inline uint16_t tlb_dsmall_size(void) |
|
- | 246 | { |
|
- | 247 | return 16; |
|
- | 248 | } |
|
- | 249 | ||
- | 250 | /** |
|
- | 251 | * Determine the number od entries in each DMMU's big TLB. |
|
- | 252 | */ |
|
- | 253 | static inline uint16_t tlb_dbig_size(void) |
|
- | 254 | { |
|
- | 255 | return 512; |
|
- | 256 | } |
|
- | 257 | ||
- | 258 | /** |
|
- | 259 | * Determine the number od entries in the IMMU's small TLB. |
|
- | 260 | */ |
|
- | 261 | static inline uint16_t tlb_ismall_size(void) |
|
- | 262 | { |
|
- | 263 | return 16; |
|
- | 264 | } |
|
- | 265 | ||
- | 266 | /** |
|
- | 267 | * Determine the number od entries in the IMMU's big TLB. |
|
- | 268 | */ |
|
- | 269 | static inline uint16_t tlb_ibig_size(void) |
|
- | 270 | { |
|
- | 271 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
|
- | 272 | return 512; |
|
- | 273 | else |
|
- | 274 | return 128; |
|
- | 275 | } |
|
- | 276 | ||
- | 277 | #endif |
|
- | 278 | ||
233 | /** Read MMU Primary Context Register. |
279 | /** Read MMU Primary Context Register. |
234 | * |
280 | * |
235 | * @return Current value of Primary Context Register. |
281 | * @return Current value of Primary Context Register. |
236 | */ |
282 | */ |
237 | static inline uint64_t mmu_primary_context_read(void) |
283 | static inline uint64_t mmu_primary_context_read(void) |
Line 363... | Line 409... | ||
363 | #elif defined (US3) |
409 | #elif defined (US3) |
364 | 410 | ||
365 | 411 | ||
366 | /** Read IMMU TLB Data Access Register. |
412 | /** Read IMMU TLB Data Access Register. |
367 | * |
413 | * |
368 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
414 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
369 | * @param entry TLB Entry index. |
415 | * @param entry TLB Entry index. |
370 | * |
416 | * |
371 | * @return Current value of specified IMMU TLB Data Access Register. |
417 | * @return Current value of specified IMMU TLB Data Access Register. |
372 | */ |
418 | */ |
373 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
419 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
Line 379... | Line 425... | ||
379 | reg.local_tlb_entry = entry; |
425 | reg.local_tlb_entry = entry; |
380 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
426 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
381 | } |
427 | } |
382 | 428 | ||
383 | /** Write IMMU TLB Data Access Register. |
429 | /** Write IMMU TLB Data Access Register. |
384 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
430 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
385 | * @param entry TLB Entry index. |
431 | * @param entry TLB Entry index. |
386 | * @param value Value to be written. |
432 | * @param value Value to be written. |
387 | */ |
433 | */ |
388 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
434 | static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
389 | { |
435 | { |
Line 396... | Line 442... | ||
396 | flush_pipeline(); |
442 | flush_pipeline(); |
397 | } |
443 | } |
398 | 444 | ||
399 | /** Read DMMU TLB Data Access Register. |
445 | /** Read DMMU TLB Data Access Register. |
400 | * |
446 | * |
401 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
447 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
402 | * @param entry TLB Entry index. |
448 | * @param entry TLB Entry index. |
403 | * |
449 | * |
404 | * @return Current value of specified DMMU TLB Data Access Register. |
450 | * @return Current value of specified DMMU TLB Data Access Register. |
405 | */ |
451 | */ |
406 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
452 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
Line 413... | Line 459... | ||
413 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
459 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
414 | } |
460 | } |
415 | 461 | ||
416 | /** Write DMMU TLB Data Access Register. |
462 | /** Write DMMU TLB Data Access Register. |
417 | * |
463 | * |
418 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
464 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
419 | * @param entry TLB Entry index. |
465 | * @param entry TLB Entry index. |
420 | * @param value Value to be written. |
466 | * @param value Value to be written. |
421 | */ |
467 | */ |
422 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
468 | static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
423 | { |
469 | { |
Line 430... | Line 476... | ||
430 | membar(); |
476 | membar(); |
431 | } |
477 | } |
432 | 478 | ||
433 | /** Read IMMU TLB Tag Read Register. |
479 | /** Read IMMU TLB Tag Read Register. |
434 | * |
480 | * |
435 | * @param tlb TLB number (one of TLB_IT16 or TLB_IT128) |
481 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
436 | * @param entry TLB Entry index. |
482 | * @param entry TLB Entry index. |
437 | * |
483 | * |
438 | * @return Current value of specified IMMU TLB Tag Read Register. |
484 | * @return Current value of specified IMMU TLB Tag Read Register. |
439 | */ |
485 | */ |
440 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
486 | static inline uint64_t itlb_tag_read_read(int tlb, index_t entry) |
Line 447... | Line 493... | ||
447 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
493 | return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
448 | } |
494 | } |
449 | 495 | ||
450 | /** Read DMMU TLB Tag Read Register. |
496 | /** Read DMMU TLB Tag Read Register. |
451 | * |
497 | * |
452 | * @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1) |
498 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) |
453 | * @param entry TLB Entry index. |
499 | * @param entry TLB Entry index. |
454 | * |
500 | * |
455 | * @return Current value of specified DMMU TLB Tag Read Register. |
501 | * @return Current value of specified DMMU TLB Tag Read Register. |
456 | */ |
502 | */ |
457 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |
503 | static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry) |