WebSVN – HelenOS – Diff – /branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h

 /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
 #if defined (US3)
 #define DTLB_MAX_LOCKED_ENTRIES     16
 #endif
+#define MEM_CONTEXT_KERNEL      0
+#define MEM_CONTEXT_TEMP        1
 /** Bit width of the TLB-locked portion of kernel address space. */
 #define KERNEL_PAGE_WIDTH       22  /* 4M */
 /* TLB Demap Operation types. */
 #define TLB_DEMAP_PAGE      0
 #include <arch/mm/page.h>
 #include <arch/asm.h>
 #include <arch/barrier.h>
 #include <arch/types.h>
 #include <arch/register.h>
-#include <arch/cpu.h>
+#include <arch/sun4u/cpu.h>
 union tlb_context_reg {
     uint64_t v;
     struct {
         unsigned long : 51;
 /*
  * In US3, I-MMU and D-MMU have different formats of the data
  * access register virtual address. In the corresponding
  * structures the member variable for the entry number is
- * called "local_tlb_entry" - it contrast with the "tlb_entry"
+ * called "local_tlb_entry" - it contrasts with the "tlb_entry"
  * for the US data access register VA structure. The rationale
  * behind this is to prevent careless mistakes in the code
  * caused by setting only the entry number and not the TLB
  * number in the US3 code (when taking the code from US).
  */
  * Functions for determining the number of entries in TLBs. They either return
  * a constant value or a value based on the CPU autodetection.
  */
 /**
- * Determine the number od entries in the DMMU's small TLB.
+ * Determine the number of entries in the DMMU's small TLB.
  */
 static inline uint16_t tlb_dsmall_size(void)
+{
     return 16;
+}
 /**
- * Determine the number od entries in each DMMU's big TLB.
+ * Determine the number of entries in each DMMU's big TLB.
  */
 static inline uint16_t tlb_dbig_size(void)
+{
     return 512;
+}
 /**
- * Determine the number od entries in the IMMU's small TLB.
+ * Determine the number of entries in the IMMU's small TLB.
  */
 static inline uint16_t tlb_ismall_size(void)
+{
     return 16;
+}
 /**
- * Determine the number od entries in the IMMU's big TLB.
+ * Determine the number of entries in the IMMU's big TLB.
  */
 static inline uint16_t tlb_ibig_size(void)
+{
     if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
         return 512;
 /** Read IMMU TLB Data Access Register.
+ *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
+ *
- * @return Current value of specified IMMU TLB Data Access Register.
+ * @return      Current value of specified IMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t itlb_data_access_read(index_t entry)
+{
     itlb_data_access_addr_t reg;
 /** Read DMMU TLB Data Access Register.
+ *
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
+ *
- * @return Current value of specified DMMU TLB Data Access Register.
+ * @return      Current value of specified DMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t dtlb_data_access_read(index_t entry)
+{
     dtlb_data_access_addr_t reg;
 /** Read IMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
+ * @param tlb       TLB number (one of TLB_ISMALL or TLB_IBIG)
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
+ *
- * @return Current value of specified IMMU TLB Data Access Register.
+ * @return      Current value of specified IMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
+{
     itlb_data_access_addr_t reg;
 /** Read DMMU TLB Data Access Register.
+ *
- * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
+ * @param tlb       TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
- * @param entry TLB Entry index.
+ * @param entry     TLB Entry index.
+ *
- * @return Current value of specified DMMU TLB Data Access Register.
+ * @return      Current value of specified DMMU TLB Data Access
+ *          Register.
  */
 static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
+{
     dtlb_data_access_addr_t reg;
     return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
+}
 /** Perform IMMU TLB Demap Operation.
+ *
- * @param type
- *  Selects between context and page demap
+ * @param type      Selects between context and page demap (and entire MMU
- *  (and entire MMU demap on US3).
+ *          demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- *  demap.
+ *          demap.
- * @param page Address which is on the page to be demapped.
+ * @param page      Address which is on the page to be demapped.
  */
 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
     da.type = type;
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
-                             * address within the
+    /* da.value is the address within the ASI */
-                             * ASI */
+    asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
     flush_pipeline();
+}
 /** Perform DMMU TLB Demap Operation.
+ *
- * @param type
- *  Selects between context and page demap
+ * @param type      Selects between context and page demap (and entire MMU
- *  (and entire MMU demap on US3).
+ *          demap on US3).
  * @param context_encoding Specifies which Context register has Context ID for
- *   demap.
+ *          demap.
- * @param page Address which is on the page to be demapped.
+ * @param page      Address which is on the page to be demapped.
  */
 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
     da.type = type;
     da.context = context_encoding;
     da.vpn = pg.vpn;
-    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
-                             * address within the
+    /* da.value is the address within the ASI */
-                             * ASI */
+    asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
     membar();
+}
-extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
+extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
-extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
+extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
-extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
+extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
-extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
+extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
-extern void dump_sfsr_and_sfar(void);
+extern void describe_mmu_fault(void);
 #endif /* !def __ASM__ */
 #endif

Subversion Repositories HelenOS

(root)/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h – Rev 3743 → 3770