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44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
44 | /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ |
45 | #if defined (US3) |
45 | #if defined (US3) |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
46 | #define DTLB_MAX_LOCKED_ENTRIES 16 |
47 | #endif |
47 | #endif |
48 | 48 | ||
- | 49 | #define MEM_CONTEXT_KERNEL 0 |
|
- | 50 | #define MEM_CONTEXT_TEMP 1 |
|
- | 51 | ||
49 | /** Bit width of the TLB-locked portion of kernel address space. */ |
52 | /** Bit width of the TLB-locked portion of kernel address space. */ |
50 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
53 | #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
51 | 54 | ||
52 | /* TLB Demap Operation types. */ |
55 | /* TLB Demap Operation types. */ |
53 | #define TLB_DEMAP_PAGE 0 |
56 | #define TLB_DEMAP_PAGE 0 |
Line 89... | Line 92... | ||
89 | #include <arch/mm/page.h> |
92 | #include <arch/mm/page.h> |
90 | #include <arch/asm.h> |
93 | #include <arch/asm.h> |
91 | #include <arch/barrier.h> |
94 | #include <arch/barrier.h> |
92 | #include <arch/types.h> |
95 | #include <arch/types.h> |
93 | #include <arch/register.h> |
96 | #include <arch/register.h> |
94 | #include <arch/cpu.h> |
97 | #include <arch/sun4u/cpu.h> |
95 | 98 | ||
96 | union tlb_context_reg { |
99 | union tlb_context_reg { |
97 | uint64_t v; |
100 | uint64_t v; |
98 | struct { |
101 | struct { |
99 | unsigned long : 51; |
102 | unsigned long : 51; |
Line 126... | Line 129... | ||
126 | 129 | ||
127 | /* |
130 | /* |
128 | * In US3, I-MMU and D-MMU have different formats of the data |
131 | * In US3, I-MMU and D-MMU have different formats of the data |
129 | * access register virtual address. In the corresponding |
132 | * access register virtual address. In the corresponding |
130 | * structures the member variable for the entry number is |
133 | * structures the member variable for the entry number is |
131 | * called "local_tlb_entry" - it contrast with the "tlb_entry" |
134 | * called "local_tlb_entry" - it contrasts with the "tlb_entry" |
132 | * for the US data access register VA structure. The rationale |
135 | * for the US data access register VA structure. The rationale |
133 | * behind this is to prevent careless mistakes in the code |
136 | * behind this is to prevent careless mistakes in the code |
134 | * caused by setting only the entry number and not the TLB |
137 | * caused by setting only the entry number and not the TLB |
135 | * number in the US3 code (when taking the code from US). |
138 | * number in the US3 code (when taking the code from US). |
136 | */ |
139 | */ |
Line 228... | Line 231... | ||
228 | * Functions for determining the number of entries in TLBs. They either return |
231 | * Functions for determining the number of entries in TLBs. They either return |
229 | * a constant value or a value based on the CPU autodetection. |
232 | * a constant value or a value based on the CPU autodetection. |
230 | */ |
233 | */ |
231 | 234 | ||
232 | /** |
235 | /** |
233 | * Determine the number od entries in the DMMU's small TLB. |
236 | * Determine the number of entries in the DMMU's small TLB. |
234 | */ |
237 | */ |
235 | static inline uint16_t tlb_dsmall_size(void) |
238 | static inline uint16_t tlb_dsmall_size(void) |
236 | { |
239 | { |
237 | return 16; |
240 | return 16; |
238 | } |
241 | } |
239 | 242 | ||
240 | /** |
243 | /** |
241 | * Determine the number od entries in each DMMU's big TLB. |
244 | * Determine the number of entries in each DMMU's big TLB. |
242 | */ |
245 | */ |
243 | static inline uint16_t tlb_dbig_size(void) |
246 | static inline uint16_t tlb_dbig_size(void) |
244 | { |
247 | { |
245 | return 512; |
248 | return 512; |
246 | } |
249 | } |
247 | 250 | ||
248 | /** |
251 | /** |
249 | * Determine the number od entries in the IMMU's small TLB. |
252 | * Determine the number of entries in the IMMU's small TLB. |
250 | */ |
253 | */ |
251 | static inline uint16_t tlb_ismall_size(void) |
254 | static inline uint16_t tlb_ismall_size(void) |
252 | { |
255 | { |
253 | return 16; |
256 | return 16; |
254 | } |
257 | } |
255 | 258 | ||
256 | /** |
259 | /** |
257 | * Determine the number od entries in the IMMU's big TLB. |
260 | * Determine the number of entries in the IMMU's big TLB. |
258 | */ |
261 | */ |
259 | static inline uint16_t tlb_ibig_size(void) |
262 | static inline uint16_t tlb_ibig_size(void) |
260 | { |
263 | { |
261 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
264 | if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) |
262 | return 512; |
265 | return 512; |
Line 308... | Line 311... | ||
308 | 311 | ||
309 | /** Read IMMU TLB Data Access Register. |
312 | /** Read IMMU TLB Data Access Register. |
310 | * |
313 | * |
311 | * @param entry TLB Entry index. |
314 | * @param entry TLB Entry index. |
312 | * |
315 | * |
313 | * @return Current value of specified IMMU TLB Data Access Register. |
316 | * @return Current value of specified IMMU TLB Data Access |
- | 317 | * Register. |
|
314 | */ |
318 | */ |
315 | static inline uint64_t itlb_data_access_read(index_t entry) |
319 | static inline uint64_t itlb_data_access_read(index_t entry) |
316 | { |
320 | { |
317 | itlb_data_access_addr_t reg; |
321 | itlb_data_access_addr_t reg; |
318 | 322 | ||
Line 338... | Line 342... | ||
338 | 342 | ||
339 | /** Read DMMU TLB Data Access Register. |
343 | /** Read DMMU TLB Data Access Register. |
340 | * |
344 | * |
341 | * @param entry TLB Entry index. |
345 | * @param entry TLB Entry index. |
342 | * |
346 | * |
343 | * @return Current value of specified DMMU TLB Data Access Register. |
347 | * @return Current value of specified DMMU TLB Data Access |
- | 348 | * Register. |
|
344 | */ |
349 | */ |
345 | static inline uint64_t dtlb_data_access_read(index_t entry) |
350 | static inline uint64_t dtlb_data_access_read(index_t entry) |
346 | { |
351 | { |
347 | dtlb_data_access_addr_t reg; |
352 | dtlb_data_access_addr_t reg; |
348 | 353 | ||
Line 402... | Line 407... | ||
402 | /** Read IMMU TLB Data Access Register. |
407 | /** Read IMMU TLB Data Access Register. |
403 | * |
408 | * |
404 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
409 | * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) |
405 | * @param entry TLB Entry index. |
410 | * @param entry TLB Entry index. |
406 | * |
411 | * |
407 | * @return Current value of specified IMMU TLB Data Access Register. |
412 | * @return Current value of specified IMMU TLB Data Access |
- | 413 | * Register. |
|
408 | */ |
414 | */ |
409 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
415 | static inline uint64_t itlb_data_access_read(int tlb, index_t entry) |
410 | { |
416 | { |
411 | itlb_data_access_addr_t reg; |
417 | itlb_data_access_addr_t reg; |
412 | 418 | ||
Line 436... | Line 442... | ||
436 | /** Read DMMU TLB Data Access Register. |
442 | /** Read DMMU TLB Data Access Register. |
437 | * |
443 | * |
438 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
444 | * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) |
439 | * @param entry TLB Entry index. |
445 | * @param entry TLB Entry index. |
440 | * |
446 | * |
441 | * @return Current value of specified DMMU TLB Data Access Register. |
447 | * @return Current value of specified DMMU TLB Data Access |
- | 448 | * Register. |
|
442 | */ |
449 | */ |
443 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
450 | static inline uint64_t dtlb_data_access_read(int tlb, index_t entry) |
444 | { |
451 | { |
445 | dtlb_data_access_addr_t reg; |
452 | dtlb_data_access_addr_t reg; |
446 | 453 | ||
Line 611... | Line 618... | ||
611 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
618 | return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
612 | } |
619 | } |
613 | 620 | ||
614 | /** Perform IMMU TLB Demap Operation. |
621 | /** Perform IMMU TLB Demap Operation. |
615 | * |
622 | * |
616 | * @param type |
- | |
617 | * Selects between context and page demap |
623 | * @param type Selects between context and page demap (and entire MMU |
618 | * (and entire MMU demap on US3). |
624 | * demap on US3). |
619 | * @param context_encoding Specifies which Context register has Context ID for |
625 | * @param context_encoding Specifies which Context register has Context ID for |
620 | * demap. |
626 | * demap. |
621 | * @param page Address which is on the page to be demapped. |
627 | * @param page Address which is on the page to be demapped. |
622 | */ |
628 | */ |
623 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
629 | static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
Line 630... | Line 636... | ||
630 | 636 | ||
631 | da.type = type; |
637 | da.type = type; |
632 | da.context = context_encoding; |
638 | da.context = context_encoding; |
633 | da.vpn = pg.vpn; |
639 | da.vpn = pg.vpn; |
634 | 640 | ||
635 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
- | |
636 | * address within the |
641 | /* da.value is the address within the ASI */ |
637 | * ASI */ |
642 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
- | 643 | ||
638 | flush_pipeline(); |
644 | flush_pipeline(); |
639 | } |
645 | } |
640 | 646 | ||
641 | /** Perform DMMU TLB Demap Operation. |
647 | /** Perform DMMU TLB Demap Operation. |
642 | * |
648 | * |
643 | * @param type |
- | |
644 | * Selects between context and page demap |
649 | * @param type Selects between context and page demap (and entire MMU |
645 | * (and entire MMU demap on US3). |
650 | * demap on US3). |
646 | * @param context_encoding Specifies which Context register has Context ID for |
651 | * @param context_encoding Specifies which Context register has Context ID for |
647 | * demap. |
652 | * demap. |
648 | * @param page Address which is on the page to be demapped. |
653 | * @param page Address which is on the page to be demapped. |
649 | */ |
654 | */ |
650 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
655 | static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
Line 657... | Line 662... | ||
657 | 662 | ||
658 | da.type = type; |
663 | da.type = type; |
659 | da.context = context_encoding; |
664 | da.context = context_encoding; |
660 | da.vpn = pg.vpn; |
665 | da.vpn = pg.vpn; |
661 | 666 | ||
662 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
- | |
663 | * address within the |
667 | /* da.value is the address within the ASI */ |
664 | * ASI */ |
668 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
- | 669 | ||
665 | membar(); |
670 | membar(); |
666 | } |
671 | } |
667 | 672 | ||
668 | extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
673 | extern void fast_instruction_access_mmu_miss(unative_t, istate_t *); |
669 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
674 | extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); |
670 | extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
675 | extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); |
671 | 676 | ||
672 | extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
677 | extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); |
673 | 678 | ||
674 | extern void dump_sfsr_and_sfar(void); |
679 | extern void describe_mmu_fault(void); |
675 | 680 | ||
676 | #endif /* !def __ASM__ */ |
681 | #endif /* !def __ASM__ */ |
677 | 682 | ||
678 | #endif |
683 | #endif |
679 | 684 |