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Rev 3386 | Rev 4153 | ||
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Line 133... | Line 133... | ||
133 | switch (b) { |
133 | switch (b) { |
134 | case 0: /*cnt 1-3*/ |
134 | case 0: /* cnt 1 - 3 */ |
135 | ps = PAGE_WIDTH; |
135 | ps = PAGE_WIDTH; |
136 | break; |
136 | break; |
137 | case 1: /*cnt 4-15*/ |
137 | case 1: /* cnt 4 - 15 */ |
138 | /*cnt=((cnt-1)/4)+1;*/ |
- | |
139 | ps = PAGE_WIDTH+2; |
138 | ps = PAGE_WIDTH + 2; |
140 | va &= ~((1<<ps)-1); |
139 | va &= ~((1 << ps) - 1); |
141 | break; |
140 | break; |
142 | case 2: /*cnt 16-63*/ |
141 | case 2: /* cnt 16 - 63 */ |
143 | /*cnt=((cnt-1)/16)+1;*/ |
- | |
144 | ps = PAGE_WIDTH+4; |
142 | ps = PAGE_WIDTH + 4; |
145 | va &= ~((1<<ps)-1); |
143 | va &= ~((1 << ps) - 1); |
146 | break; |
144 | break; |
147 | case 3: /*cnt 64-255*/ |
145 | case 3: /* cnt 64 - 255 */ |
148 | /*cnt=((cnt-1)/64)+1;*/ |
- | |
149 | ps = PAGE_WIDTH+6; |
146 | ps = PAGE_WIDTH + 6; |
150 | va &= ~((1<<ps)-1); |
147 | va &= ~((1 << ps) - 1); |
151 | break; |
148 | break; |
152 | case 4: /*cnt 256-1023*/ |
149 | case 4: /* cnt 256 - 1023 */ |
153 | /*cnt=((cnt-1)/256)+1;*/ |
- | |
154 | ps = PAGE_WIDTH+8; |
150 | ps = PAGE_WIDTH + 8; |
155 | va &= ~((1<<ps)-1); |
151 | va &= ~((1 << ps) - 1); |
156 | break; |
152 | break; |
157 | case 5: /*cnt 1024-4095*/ |
153 | case 5: /* cnt 1024 - 4095 */ |
158 | /*cnt=((cnt-1)/1024)+1;*/ |
- | |
159 | ps = PAGE_WIDTH+10; |
154 | ps = PAGE_WIDTH + 10; |
160 | va &= ~((1<<ps)-1); |
155 | va &= ~((1 << ps) - 1); |
161 | break; |
156 | break; |
162 | case 6: /*cnt 4096-16383*/ |
157 | case 6: /* cnt 4096 - 16383 */ |
163 | /*cnt=((cnt-1)/4096)+1;*/ |
- | |
164 | ps = PAGE_WIDTH+12; |
158 | ps = PAGE_WIDTH + 12; |
165 | va &= ~((1<<ps)-1); |
159 | va &= ~((1 << ps) - 1); |
166 | break; |
160 | break; |
167 | case 7: /*cnt 16384-65535*/ |
161 | case 7: /* cnt 16384 - 65535 */ |
168 | case 8: /*cnt 65536-(256K-1)*/ |
162 | case 8: /* cnt 65536 - (256K - 1) */ |
169 | /*cnt=((cnt-1)/16384)+1;*/ |
- | |
170 | ps = PAGE_WIDTH+14; |
163 | ps = PAGE_WIDTH + 14; |
171 | va &= ~((1<<ps)-1); |
164 | va &= ~((1 << ps) - 1); |
172 | break; |
165 | break; |
173 | default: |
166 | default: |
174 | /*cnt=((cnt-1)/(16384*16))+1;*/ |
- | |
175 | ps=PAGE_WIDTH+18; |
167 | ps = PAGE_WIDTH + 18; |
176 | va&=~((1<<ps)-1); |
168 | va &= ~((1 << ps) - 1); |
177 | break; |
169 | break; |
178 | } |
170 | } |
179 | /*cnt+=(page!=va);*/ |
- | |
180 | for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { |
171 | for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) |
181 | asm volatile ( |
- | |
182 | "ptc.l %0,%1;;" |
- | |
183 | : |
- | |
184 | : "r" (va), "r" (ps<<2) |
172 | asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2)); |
185 | ); |
- | |
186 | } |
- | |
187 | srlz_d(); |
173 | srlz_d(); |
188 | srlz_i(); |
174 | srlz_i(); |
189 | 175 | ||
190 | if (restore_rr) { |
176 | if (restore_rr) { |
191 | rr_write(VA2VRN(va), rr.word); |
177 | rr_write(VA2VRN(va), rr.word); |
Line 196... | Line 182... | ||
196 | 182 | ||
197 | /** Insert data into data translation cache. |
183 | /** Insert data into data translation cache. |
198 | * |
184 | * |
199 | * @param va Virtual page address. |
185 | * @param va Virtual page address. |
200 | * @param asid Address space identifier. |
186 | * @param asid Address space identifier. |
201 | * @param entry The rest of TLB entry as required by TLB insertion format. |
187 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 188 | * format. |
|
202 | */ |
189 | */ |
203 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
190 | void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
204 | { |
191 | { |
205 | tc_mapping_insert(va, asid, entry, true); |
192 | tc_mapping_insert(va, asid, entry, true); |
206 | } |
193 | } |
207 | 194 | ||
208 | /** Insert data into instruction translation cache. |
195 | /** Insert data into instruction translation cache. |
209 | * |
196 | * |
210 | * @param va Virtual page address. |
197 | * @param va Virtual page address. |
211 | * @param asid Address space identifier. |
198 | * @param asid Address space identifier. |
212 | * @param entry The rest of TLB entry as required by TLB insertion format. |
199 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 200 | * format. |
|
213 | */ |
201 | */ |
214 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
202 | void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
215 | { |
203 | { |
216 | tc_mapping_insert(va, asid, entry, false); |
204 | tc_mapping_insert(va, asid, entry, false); |
217 | } |
205 | } |
218 | 206 | ||
219 | /** Insert data into instruction or data translation cache. |
207 | /** Insert data into instruction or data translation cache. |
220 | * |
208 | * |
221 | * @param va Virtual page address. |
209 | * @param va Virtual page address. |
222 | * @param asid Address space identifier. |
210 | * @param asid Address space identifier. |
223 | * @param entry The rest of TLB entry as required by TLB insertion format. |
211 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 212 | * format. |
|
224 | * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
213 | * @param dtc If true, insert into data translation cache, use |
- | 214 | * instruction translation cache otherwise. |
|
225 | */ |
215 | */ |
226 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
216 | void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
227 | { |
217 | { |
228 | region_register rr; |
218 | region_register rr; |
229 | bool restore_rr = false; |
219 | bool restore_rr = false; |
Line 254... | Line 244... | ||
254 | "(p6) itc.i %3;;\n" |
244 | "(p6) itc.i %3;;\n" |
255 | "(p7) itc.d %3;;\n" |
245 | "(p7) itc.d %3;;\n" |
256 | "mov psr.l=r8;;\n" |
246 | "mov psr.l = r8;;\n" |
257 | "srlz.d;;\n" |
247 | "srlz.d;;\n" |
258 | : |
248 | : |
259 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc) |
249 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
- | 250 | "r" (entry.word[0]), "r" (dtc) |
|
260 | : "p6", "p7", "r8" |
251 | : "p6", "p7", "r8" |
261 | ); |
252 | ); |
262 | 253 | ||
263 | if (restore_rr) { |
254 | if (restore_rr) { |
264 | rr_write(VA2VRN(va), rr.word); |
255 | rr_write(VA2VRN(va), rr.word); |
Line 269... | Line 260... | ||
269 | 260 | ||
270 | /** Insert data into instruction translation register. |
261 | /** Insert data into instruction translation register. |
271 | * |
262 | * |
272 | * @param va Virtual page address. |
263 | * @param va Virtual page address. |
273 | * @param asid Address space identifier. |
264 | * @param asid Address space identifier. |
274 | * @param entry The rest of TLB entry as required by TLB insertion format. |
265 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 266 | * format. |
|
275 | * @param tr Translation register. |
267 | * @param tr Translation register. |
276 | */ |
268 | */ |
- | 269 | void |
|
277 | void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
270 | itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
278 | { |
271 | { |
279 | tr_mapping_insert(va, asid, entry, false, tr); |
272 | tr_mapping_insert(va, asid, entry, false, tr); |
280 | } |
273 | } |
281 | 274 | ||
282 | /** Insert data into data translation register. |
275 | /** Insert data into data translation register. |
283 | * |
276 | * |
284 | * @param va Virtual page address. |
277 | * @param va Virtual page address. |
285 | * @param asid Address space identifier. |
278 | * @param asid Address space identifier. |
286 | * @param entry The rest of TLB entry as required by TLB insertion format. |
279 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 280 | * format. |
|
287 | * @param tr Translation register. |
281 | * @param tr Translation register. |
288 | */ |
282 | */ |
- | 283 | void |
|
289 | void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
284 | dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
290 | { |
285 | { |
291 | tr_mapping_insert(va, asid, entry, true, tr); |
286 | tr_mapping_insert(va, asid, entry, true, tr); |
292 | } |
287 | } |
293 | 288 | ||
294 | /** Insert data into instruction or data translation register. |
289 | /** Insert data into instruction or data translation register. |
295 | * |
290 | * |
296 | * @param va Virtual page address. |
291 | * @param va Virtual page address. |
297 | * @param asid Address space identifier. |
292 | * @param asid Address space identifier. |
298 | * @param entry The rest of TLB entry as required by TLB insertion format. |
293 | * @param entry The rest of TLB entry as required by TLB insertion |
- | 294 | * format. |
|
299 | * @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
295 | * @param dtr If true, insert into data translation register, use |
- | 296 | * instruction translation register otherwise. |
|
300 | * @param tr Translation register. |
297 | * @param tr Translation register. |
301 | */ |
298 | */ |
- | 299 | void |
|
302 | void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
300 | tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, |
- | 301 | index_t tr) |
|
303 | { |
302 | { |
304 | region_register rr; |
303 | region_register rr; |
305 | bool restore_rr = false; |
304 | bool restore_rr = false; |
306 | 305 | ||
307 | rr.word = rr_read(VA2VRN(va)); |
306 | rr.word = rr_read(VA2VRN(va)); |
Line 330... | Line 329... | ||
330 | "(p6) itr.i itr[%4]=%3;;\n" |
329 | "(p6) itr.i itr[%4] = %3;;\n" |
331 | "(p7) itr.d dtr[%4]=%3;;\n" |
330 | "(p7) itr.d dtr[%4] = %3;;\n" |
332 | "mov psr.l=r8;;\n" |
331 | "mov psr.l = r8;;\n" |
333 | "srlz.d;;\n" |
332 | "srlz.d;;\n" |
334 | : |
333 | : |
335 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr) |
334 | : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
- | 335 | "r" (entry.word[0]), "r" (tr), "r" (dtr) |
|
336 | : "p6", "p7", "r8" |
336 | : "p6", "p7", "r8" |
337 | ); |
337 | ); |
338 | 338 | ||
339 | if (restore_rr) { |
339 | if (restore_rr) { |
340 | rr_write(VA2VRN(va), rr.word); |
340 | rr_write(VA2VRN(va), rr.word); |
Line 345... | Line 345... | ||
345 | 345 | ||
346 | /** Insert data into DTLB. |
346 | /** Insert data into DTLB. |
347 | * |
347 | * |
348 | * @param page Virtual page address including VRN bits. |
348 | * @param page Virtual page address including VRN bits. |
349 | * @param frame Physical frame address. |
349 | * @param frame Physical frame address. |
350 | * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
350 | * @param dtr If true, insert into data translation register, use data |
- | 351 | * translation cache otherwise. |
|
351 | * @param tr Translation register if dtr is true, ignored otherwise. |
352 | * @param tr Translation register if dtr is true, ignored otherwise. |
352 | */ |
353 | */ |
- | 354 | void |
|
353 | void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr) |
355 | dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, |
- | 356 | index_t tr) |
|
354 | { |
357 | { |
355 | tlb_entry_t entry; |
358 | tlb_entry_t entry; |
356 | 359 | ||
357 | entry.word[0] = 0; |
360 | entry.word[0] = 0; |
358 | entry.word[1] = 0; |
361 | entry.word[1] = 0; |
Line 467... | Line 470... | ||
467 | /* |
470 | /* |
468 | * Forward the page fault to address space page fault handler. |
471 | * Forward the page fault to address space page fault handler. |
469 | */ |
472 | */ |
470 | page_table_unlock(AS, true); |
473 | page_table_unlock(AS, true); |
471 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
474 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
472 | fault_if_from_uspace(istate,"Page fault at %p",va); |
475 | fault_if_from_uspace(istate,"Page fault at %p.",va); |
473 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
476 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, |
- | 477 | istate->cr_iip); |
|
- | 478 | } |
|
- | 479 | } |
|
- | 480 | } |
|
- | 481 | ||
- | 482 | static int is_io_page_accessible(int page) |
|
- | 483 | { |
|
- | 484 | if (TASK->arch.iomap) |
|
- | 485 | return bitmap_get(TASK->arch.iomap, page); |
|
- | 486 | else |
|
- | 487 | return 0; |
|
- | 488 | } |
|
- | 489 | ||
- | 490 | #define IO_FRAME_BASE 0xFFFFC000000 |
|
- | 491 | ||
- | 492 | /** |
|
- | 493 | * There is special handling of memory mapped legacy io, because of 4KB sized |
|
- | 494 | * access for userspace. |
|
- | 495 | * |
|
- | 496 | * @param va Virtual address of page fault. |
|
- | 497 | * @param istate Structure with saved interruption state. |
|
- | 498 | * |
|
- | 499 | * @return One on success, zero on failure. |
|
- | 500 | */ |
|
- | 501 | static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) |
|
- | 502 | { |
|
- | 503 | if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) { |
|
- | 504 | if (TASK) { |
|
- | 505 | uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >> |
|
- | 506 | USPACE_IO_PAGE_WIDTH; |
|
- | 507 | ||
- | 508 | if (is_io_page_accessible(io_page)) { |
|
- | 509 | uint64_t page, frame; |
|
- | 510 | ||
- | 511 | page = IO_OFFSET + |
|
- | 512 | (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
|
- | 513 | frame = IO_FRAME_BASE + |
|
- | 514 | (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
|
- | 515 | ||
- | 516 | tlb_entry_t entry; |
|
- | 517 | ||
- | 518 | entry.word[0] = 0; |
|
- | 519 | entry.word[1] = 0; |
|
- | 520 | ||
- | 521 | entry.p = true; /* present */ |
|
- | 522 | entry.ma = MA_UNCACHEABLE; |
|
- | 523 | entry.a = true; /* already accessed */ |
|
- | 524 | entry.d = true; /* already dirty */ |
|
- | 525 | entry.pl = PL_USER; |
|
- | 526 | entry.ar = AR_READ | AR_WRITE; |
|
- | 527 | entry.ppn = frame >> PPN_SHIFT; |
|
- | 528 | entry.ps = USPACE_IO_PAGE_WIDTH; |
|
- | 529 | ||
- | 530 | dtc_mapping_insert(page, TASK->as->asid, entry); |
|
- | 531 | return 1; |
|
- | 532 | } else { |
|
- | 533 | fault_if_from_uspace(istate, |
|
- | 534 | "IO access fault at %p.", va); |
|
- | 535 | } |
|
474 | } |
536 | } |
475 | } |
537 | } |
- | 538 | ||
- | 539 | return 0; |
|
476 | } |
540 | } |
477 | 541 | ||
478 | /** Data TLB fault handler for faults with VHPT turned off. |
542 | /** Data TLB fault handler for faults with VHPT turned off. |
479 | * |
543 | * |
480 | * @param vector Interruption vector. |
544 | * @param vector Interruption vector. |
Line 509... | Line 573... | ||
509 | * Insert it into data translation cache. |
573 | * Insert it into data translation cache. |
510 | */ |
574 | */ |
511 | dtc_pte_copy(t); |
575 | dtc_pte_copy(t); |
512 | page_table_unlock(AS, true); |
576 | page_table_unlock(AS, true); |
513 | } else { |
577 | } else { |
- | 578 | page_table_unlock(AS, true); |
|
- | 579 | if (try_memmap_io_insertion(va, istate)) |
|
- | 580 | return; |
|
514 | /* |
581 | /* |
515 | * Forward the page fault to the address space page fault handler. |
582 | * Forward the page fault to the address space page fault |
- | 583 | * handler. |
|
516 | */ |
584 | */ |
517 | page_table_unlock(AS, true); |
- | |
518 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
585 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
519 | fault_if_from_uspace(istate,"Page fault at %p",va); |
586 | fault_if_from_uspace(istate,"Page fault at %p.",va); |
520 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
587 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, |
- | 588 | istate->cr_iip); |
|
521 | } |
589 | } |
522 | } |
590 | } |
523 | } |
591 | } |
524 | 592 | ||
525 | /** Data nested TLB fault handler. |
593 | /** Data nested TLB fault handler. |
Line 529... | Line 597... | ||
529 | * @param vector Interruption vector. |
597 | * @param vector Interruption vector. |
530 | * @param istate Structure with saved interruption state. |
598 | * @param istate Structure with saved interruption state. |
531 | */ |
599 | */ |
532 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
600 | void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
533 | { |
601 | { |
534 | panic("%s\n", __func__); |
602 | panic("%s.", __func__); |
535 | } |
603 | } |
536 | 604 | ||
537 | /** Data Dirty bit fault handler. |
605 | /** Data Dirty bit fault handler. |
538 | * |
606 | * |
539 | * @param vector Interruption vector. |
607 | * @param vector Interruption vector. |
Line 560... | Line 628... | ||
560 | */ |
628 | */ |
561 | t->d = true; |
629 | t->d = true; |
562 | dtc_pte_copy(t); |
630 | dtc_pte_copy(t); |
563 | } else { |
631 | } else { |
564 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
632 | if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
565 | fault_if_from_uspace(istate,"Page fault at %p",va); |
633 | fault_if_from_uspace(istate,"Page fault at %p.",va); |
566 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
634 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, |
567 | t->d = true; |
- | |
568 | dtc_pte_copy(t); |
635 | istate->cr_iip); |
569 | } |
636 | } |
570 | } |
637 | } |
571 | page_table_unlock(AS, true); |
638 | page_table_unlock(AS, true); |
572 | } |
639 | } |
573 | 640 | ||
Line 597... | Line 664... | ||
597 | */ |
664 | */ |
598 | t->a = true; |
665 | t->a = true; |
599 | itc_pte_copy(t); |
666 | itc_pte_copy(t); |
600 | } else { |
667 | } else { |
601 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
668 | if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
602 | fault_if_from_uspace(istate,"Page fault at %p",va); |
669 | fault_if_from_uspace(istate, "Page fault at %p.", va); |
603 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
670 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, |
604 | t->a = true; |
- | |
605 | itc_pte_copy(t); |
671 | istate->cr_iip); |
606 | } |
672 | } |
607 | } |
673 | } |
608 | page_table_unlock(AS, true); |
674 | page_table_unlock(AS, true); |
609 | } |
675 | } |
610 | 676 | ||
Line 634... | Line 700... | ||
634 | */ |
700 | */ |
635 | t->a = true; |
701 | t->a = true; |
636 | dtc_pte_copy(t); |
702 | dtc_pte_copy(t); |
637 | } else { |
703 | } else { |
638 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
704 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
639 | fault_if_from_uspace(istate,"Page fault at %p",va); |
705 | fault_if_from_uspace(istate, "Page fault at %p.", va); |
640 | panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
706 | panic("%s: va=%p, rid=%d, iip=%p.", __func__, va, rid, |
641 | t->a = true; |
- | |
642 | itc_pte_copy(t); |
707 | istate->cr_iip); |
643 | } |
708 | } |
644 | } |
709 | } |
645 | page_table_unlock(AS, true); |
710 | page_table_unlock(AS, true); |
646 | } |
711 | } |
647 | 712 | ||
Line 676... | Line 741... | ||
676 | dtc_pte_copy(t); |
741 | dtc_pte_copy(t); |
677 | page_table_unlock(AS, true); |
742 | page_table_unlock(AS, true); |
678 | } else { |
743 | } else { |
679 | page_table_unlock(AS, true); |
744 | page_table_unlock(AS, true); |
680 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
745 | if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
681 | fault_if_from_uspace(istate,"Page fault at %p",va); |
746 | fault_if_from_uspace(istate, "Page fault at %p.", va); |
682 | panic("%s: va=%p, rid=%d\n", __func__, va, rid); |
747 | panic("%s: va=%p, rid=%d.", __func__, va, rid); |
683 | } |
748 | } |
684 | } |
749 | } |
685 | } |
750 | } |
686 | 751 | ||
- | 752 | void tlb_arch_init(void) |
|
- | 753 | { |
|
- | 754 | } |
|
- | 755 | ||
- | 756 | void tlb_print(void) |
|
- | 757 | { |
|
- | 758 | } |
|
- | 759 | ||
687 | /** @} |
760 | /** @} |
688 | */ |
761 | */ |