Rev 3022 | Rev 4156 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 3022 | Rev 4055 | ||
---|---|---|---|
Line 33... | Line 33... | ||
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <mm/tlb.h> |
35 | #include <mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
36 | #include <arch/mm/tlb.h> |
37 | #include <arch/interrupt.h> |
37 | #include <arch/interrupt.h> |
- | 38 | #include <interrupt.h> |
|
38 | #include <mm/as.h> |
39 | #include <mm/as.h> |
39 | #include <arch.h> |
40 | #include <arch.h> |
40 | #include <print.h> |
41 | #include <print.h> |
41 | #include <symtab.h> |
42 | #include <symtab.h> |
- | 43 | #include <macros.h> |
|
- | 44 | ||
- | 45 | ||
- | 46 | static unsigned int seed = 10; |
|
- | 47 | static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42; |
|
- | 48 | ||
- | 49 | ||
- | 50 | #define TLB_FLUSH \ |
|
- | 51 | "tlbie %0\n" \ |
|
- | 52 | "addi %0, %0, 0x1000\n" |
|
42 | 53 | ||
43 | 54 | ||
44 | /** Try to find PTE for faulting address |
55 | /** Try to find PTE for faulting address |
45 | * |
56 | * |
46 | * Try to find PTE for faulting address. |
57 | * Try to find PTE for faulting address. |
Line 50... | Line 61... | ||
50 | * @param as Address space. |
61 | * @param as Address space. |
51 | * @param lock Lock/unlock the address space. |
62 | * @param lock Lock/unlock the address space. |
52 | * @param badvaddr Faulting virtual address. |
63 | * @param badvaddr Faulting virtual address. |
53 | * @param access Access mode that caused the fault. |
64 | * @param access Access mode that caused the fault. |
54 | * @param istate Pointer to interrupted state. |
65 | * @param istate Pointer to interrupted state. |
55 | * @param pfrc Pointer to variable where as_page_fault() return code will be stored. |
66 | * @param pfrc Pointer to variable where as_page_fault() return code |
- | 67 | * will be stored. |
|
56 | * @return PTE on success, NULL otherwise. |
68 | * @return PTE on success, NULL otherwise. |
57 | * |
69 | * |
58 | */ |
70 | */ |
- | 71 | static pte_t * |
|
59 | static pte_t *find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, istate_t *istate, int *pfrc) |
72 | find_mapping_and_check(as_t *as, bool lock, uintptr_t badvaddr, int access, |
- | 73 | istate_t *istate, int *pfrc) |
|
60 | { |
74 | { |
61 | /* |
75 | /* |
62 | * Check if the mapping exists in page tables. |
76 | * Check if the mapping exists in page tables. |
63 | */ |
77 | */ |
64 | pte_t *pte = page_mapping_find(as, badvaddr); |
78 | pte_t *pte = page_mapping_find(as, badvaddr); |
65 | if ((pte) && (pte->p)) { |
79 | if ((pte) && (pte->present)) { |
66 | /* |
80 | /* |
67 | * Mapping found in page tables. |
81 | * Mapping found in page tables. |
68 | * Immediately succeed. |
82 | * Immediately succeed. |
69 | */ |
83 | */ |
70 | return pte; |
84 | return pte; |
Line 82... | Line 96... | ||
82 | * The higher-level page fault handler succeeded, |
96 | * The higher-level page fault handler succeeded, |
83 | * The mapping ought to be in place. |
97 | * The mapping ought to be in place. |
84 | */ |
98 | */ |
85 | page_table_lock(as, lock); |
99 | page_table_lock(as, lock); |
86 | pte = page_mapping_find(as, badvaddr); |
100 | pte = page_mapping_find(as, badvaddr); |
87 | ASSERT((pte) && (pte->p)); |
101 | ASSERT((pte) && (pte->present)); |
88 | *pfrc = 0; |
102 | *pfrc = 0; |
89 | return pte; |
103 | return pte; |
90 | case AS_PF_DEFER: |
104 | case AS_PF_DEFER: |
91 | page_table_lock(as, lock); |
105 | page_table_lock(as, lock); |
92 | *pfrc = rc; |
106 | *pfrc = rc; |
93 | return NULL; |
107 | return NULL; |
94 | case AS_PF_FAULT: |
108 | case AS_PF_FAULT: |
95 | page_table_lock(as, lock); |
109 | page_table_lock(as, lock); |
96 | printf("Page fault.\n"); |
- | |
97 | *pfrc = rc; |
110 | *pfrc = rc; |
98 | return NULL; |
111 | return NULL; |
99 | default: |
112 | default: |
100 | panic("unexpected rc (%d)\n", rc); |
113 | panic("Unexpected rc (%d).", rc); |
101 | } |
114 | } |
102 | } |
115 | } |
103 | } |
116 | } |
104 | 117 | ||
105 | 118 | ||
106 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
119 | static void pht_refill_fail(uintptr_t badvaddr, istate_t *istate) |
107 | { |
120 | { |
108 | char *symbol = ""; |
121 | char *symbol = ""; |
109 | char *sym2 = ""; |
122 | char *sym2 = ""; |
110 | 123 | ||
111 | char *s = get_symtab_entry(istate->pc); |
124 | char *str = get_symtab_entry(istate->pc); |
112 | if (s) |
125 | if (str) |
113 | symbol = s; |
126 | symbol = str; |
114 | s = get_symtab_entry(istate->lr); |
127 | str = get_symtab_entry(istate->lr); |
115 | if (s) |
128 | if (str) |
116 | sym2 = s; |
129 | sym2 = str; |
- | 130 | ||
- | 131 | fault_if_from_uspace(istate, |
|
- | 132 | "PHT Refill Exception on %p.", badvaddr); |
|
117 | panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2); |
133 | panic("%p: PHT Refill Exception at %p (%s<-%s).", badvaddr, |
- | 134 | istate->pc, symbol, sym2); |
|
118 | } |
135 | } |
119 | 136 | ||
120 | 137 | ||
121 | static void pht_insert(const uintptr_t vaddr, const pfn_t pfn) |
138 | static void pht_insert(const uintptr_t vaddr, const pte_t *pte) |
122 | { |
139 | { |
123 | uint32_t page = (vaddr >> 12) & 0xffff; |
140 | uint32_t page = (vaddr >> 12) & 0xffff; |
124 | uint32_t api = (vaddr >> 22) & 0x3f; |
141 | uint32_t api = (vaddr >> 22) & 0x3f; |
125 | 142 | ||
126 | uint32_t vsid; |
143 | uint32_t vsid; |
Line 142... | Line 159... | ||
142 | uint32_t hash = vsid ^ page; |
159 | uint32_t hash = vsid ^ page; |
143 | uint32_t base = (hash & 0x3ff) << 3; |
160 | uint32_t base = (hash & 0x3ff) << 3; |
144 | uint32_t i; |
161 | uint32_t i; |
145 | bool found = false; |
162 | bool found = false; |
146 | 163 | ||
147 | /* Find unused or colliding |
- | |
148 | PTE in PTEG */ |
164 | /* Find colliding PTE in PTEG */ |
149 | for (i = 0; i < 8; i++) { |
165 | for (i = 0; i < 8; i++) { |
- | 166 | if ((phte[base + i].v) |
|
150 | if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) { |
167 | && (phte[base + i].vsid == vsid) |
- | 168 | && (phte[base + i].api == api) |
|
- | 169 | && (phte[base + i].h == 0)) { |
|
151 | found = true; |
170 | found = true; |
152 | break; |
171 | break; |
153 | } |
172 | } |
154 | } |
173 | } |
155 | 174 | ||
156 | if (!found) { |
175 | if (!found) { |
157 | /* Secondary hash (not) */ |
- | |
158 | uint32_t base2 = (~hash & 0x3ff) << 3; |
- | |
159 | - | ||
160 | /* Find unused or colliding |
176 | /* Find unused PTE in PTEG */ |
161 | PTE in PTEG */ |
- | |
162 | for (i = 0; i < 8; i++) { |
177 | for (i = 0; i < 8; i++) { |
163 | if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) { |
178 | if (!phte[base + i].v) { |
164 | found = true; |
179 | found = true; |
165 | base = base2; |
- | |
166 | h = 1; |
- | |
167 | break; |
180 | break; |
168 | } |
181 | } |
169 | } |
182 | } |
170 | - | ||
171 | if (!found) { |
- | |
172 | // TODO: A/C precedence groups |
- | |
173 | i = page % 8; |
- | |
174 | } |
- | |
175 | } |
- | |
176 | - | ||
177 | phte[base + i].v = 1; |
- | |
178 | phte[base + i].vsid = vsid; |
- | |
179 | phte[base + i].h = h; |
- | |
180 | phte[base + i].api = api; |
- | |
181 | phte[base + i].rpn = pfn; |
- | |
182 | phte[base + i].r = 0; |
- | |
183 | phte[base + i].c = 0; |
- | |
184 | phte[base + i].pp = 2; // FIXME |
- | |
185 | } |
183 | } |
186 | 184 | ||
- | 185 | if (!found) { |
|
- | 186 | /* Secondary hash (not) */ |
|
- | 187 | uint32_t base2 = (~hash & 0x3ff) << 3; |
|
187 | 188 | ||
188 | static void pht_real_insert(const uintptr_t vaddr, const pfn_t pfn) |
- | |
189 | { |
- | |
190 | uint32_t page = (vaddr >> 12) & 0xffff; |
- | |
191 | uint32_t api = (vaddr >> 22) & 0x3f; |
- | |
192 | - | ||
193 | uint32_t vsid; |
- | |
194 | asm volatile ( |
- | |
195 | "mfsrin %0, %1\n" |
- | |
196 | : "=r" (vsid) |
- | |
197 | : "r" (vaddr) |
- | |
198 | ); |
- | |
199 | - | ||
200 | uint32_t sdr1; |
- | |
201 | asm volatile ( |
- | |
202 | "mfsdr1 %0\n" |
- | |
203 | : "=r" (sdr1) |
- | |
204 | ); |
- | |
205 | phte_t *phte_physical = (phte_t *) (sdr1 & 0xffff0000); |
- | |
206 | - | ||
207 | /* Primary hash (xor) */ |
- | |
208 | uint32_t h = 0; |
- | |
209 | uint32_t hash = vsid ^ page; |
- | |
210 | uint32_t base = (hash & 0x3ff) << 3; |
- | |
211 | uint32_t i; |
- | |
212 | bool found = false; |
- | |
213 | - | ||
214 | /* Find unused or colliding |
- | |
215 | PTE in PTEG */ |
189 | /* Find colliding PTE in PTEG */ |
216 | for (i = 0; i < 8; i++) { |
190 | for (i = 0; i < 8; i++) { |
- | 191 | if ((phte[base2 + i].v) |
|
217 | if ((!phte_physical[base + i].v) || ((phte_physical[base + i].vsid == vsid) && (phte_physical[base + i].api == api))) { |
192 | && (phte[base2 + i].vsid == vsid) |
- | 193 | && (phte[base2 + i].api == api) |
|
- | 194 | && (phte[base2 + i].h == 1)) { |
|
218 | found = true; |
195 | found = true; |
- | 196 | base = base2; |
|
- | 197 | h = 1; |
|
219 | break; |
198 | break; |
220 | } |
199 | } |
221 | } |
200 | } |
222 | 201 | ||
223 | if (!found) { |
202 | if (!found) { |
224 | /* Secondary hash (not) */ |
- | |
225 | uint32_t base2 = (~hash & 0x3ff) << 3; |
- | |
226 | - | ||
227 | /* Find unused or colliding |
203 | /* Find unused PTE in PTEG */ |
228 | PTE in PTEG */ |
- | |
229 | for (i = 0; i < 8; i++) { |
204 | for (i = 0; i < 8; i++) { |
230 | if ((!phte_physical[base2 + i].v) || ((phte_physical[base2 + i].vsid == vsid) && (phte_physical[base2 + i].api == api))) { |
205 | if (!phte[base2 + i].v) { |
231 | found = true; |
206 | found = true; |
232 | base = base2; |
207 | base = base2; |
233 | h = 1; |
208 | h = 1; |
234 | break; |
209 | break; |
235 | } |
210 | } |
236 | } |
211 | } |
237 | - | ||
238 | if (!found) { |
- | |
239 | // TODO: A/C precedence groups |
- | |
240 | i = page % 8; |
- | |
241 | } |
212 | } |
- | 213 | ||
- | 214 | if (!found) |
|
- | 215 | i = RANDI(seed) % 8; |
|
242 | } |
216 | } |
243 | 217 | ||
244 | phte_physical[base + i].v = 1; |
218 | phte[base + i].v = 1; |
245 | phte_physical[base + i].vsid = vsid; |
219 | phte[base + i].vsid = vsid; |
246 | phte_physical[base + i].h = h; |
220 | phte[base + i].h = h; |
247 | phte_physical[base + i].api = api; |
221 | phte[base + i].api = api; |
248 | phte_physical[base + i].rpn = pfn; |
222 | phte[base + i].rpn = pte->pfn; |
249 | phte_physical[base + i].r = 0; |
223 | phte[base + i].r = 0; |
250 | phte_physical[base + i].c = 0; |
224 | phte[base + i].c = 0; |
- | 225 | phte[base + i].wimg = (pte->page_cache_disable ? WIMG_NO_CACHE : 0); |
|
251 | phte_physical[base + i].pp = 2; // FIXME |
226 | phte[base + i].pp = 2; // FIXME |
252 | } |
227 | } |
253 | 228 | ||
254 | 229 | ||
255 | /** Process Instruction/Data Storage Interrupt |
230 | /** Process Instruction/Data Storage Exception |
256 | * |
231 | * |
257 | * @param n Interrupt vector number. |
232 | * @param n Exception vector number. |
258 | * @param istate Interrupted register context. |
233 | * @param istate Interrupted register context. |
259 | * |
234 | * |
260 | */ |
235 | */ |
261 | void pht_refill(int n, istate_t *istate) |
236 | void pht_refill(int n, istate_t *istate) |
262 | { |
237 | { |
Line 272... | Line 247... | ||
272 | } else { |
247 | } else { |
273 | as = AS; |
248 | as = AS; |
274 | lock = true; |
249 | lock = true; |
275 | } |
250 | } |
276 | 251 | ||
277 | if (n == VECTOR_DATA_STORAGE) { |
252 | if (n == VECTOR_DATA_STORAGE) |
278 | asm volatile ( |
- | |
279 | "mfdar %0\n" |
- | |
280 | : "=r" (badvaddr) |
253 | badvaddr = istate->dar; |
281 | ); |
- | |
282 | } else |
254 | else |
283 | badvaddr = istate->pc; |
255 | badvaddr = istate->pc; |
284 | 256 | ||
285 | page_table_lock(as, lock); |
257 | page_table_lock(as, lock); |
286 | 258 | ||
287 | pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
259 | pte = find_mapping_and_check(as, lock, badvaddr, |
- | 260 | PF_ACCESS_READ /* FIXME */, istate, &pfrc); |
|
288 | if (!pte) { |
261 | if (!pte) { |
289 | switch (pfrc) { |
262 | switch (pfrc) { |
290 | case AS_PF_FAULT: |
263 | case AS_PF_FAULT: |
291 | goto fail; |
264 | goto fail; |
292 | break; |
265 | break; |
Line 296... | Line 269... | ||
296 | * or copy_to_uspace(). |
269 | * or copy_to_uspace(). |
297 | */ |
270 | */ |
298 | page_table_unlock(as, lock); |
271 | page_table_unlock(as, lock); |
299 | return; |
272 | return; |
300 | default: |
273 | default: |
301 | panic("Unexpected pfrc (%d)\n", pfrc); |
274 | panic("Unexpected pfrc (%d).", pfrc); |
302 | } |
275 | } |
303 | } |
276 | } |
304 | 277 | ||
305 | pte->a = 1; /* Record access to PTE */ |
278 | pte->accessed = 1; /* Record access to PTE */ |
306 | pht_insert(badvaddr, pte->pfn); |
279 | pht_insert(badvaddr, pte); |
307 | 280 | ||
308 | page_table_unlock(as, lock); |
281 | page_table_unlock(as, lock); |
309 | return; |
282 | return; |
310 | 283 | ||
311 | fail: |
284 | fail: |
312 | page_table_unlock(as, lock); |
285 | page_table_unlock(as, lock); |
313 | pht_refill_fail(badvaddr, istate); |
286 | pht_refill_fail(badvaddr, istate); |
314 | } |
287 | } |
315 | 288 | ||
316 | 289 | ||
317 | /** Process Instruction/Data Storage Interrupt in Real Mode |
290 | /** Process Instruction/Data Storage Exception in Real Mode |
318 | * |
291 | * |
319 | * @param n Interrupt vector number. |
292 | * @param n Exception vector number. |
320 | * @param istate Interrupted register context. |
293 | * @param istate Interrupted register context. |
321 | * |
294 | * |
322 | */ |
295 | */ |
323 | bool pht_real_refill(int n, istate_t *istate) |
296 | bool pht_refill_real(int n, istate_t *istate) |
324 | { |
297 | { |
325 | uintptr_t badvaddr; |
298 | uintptr_t badvaddr; |
326 | 299 | ||
327 | if (n == VECTOR_DATA_STORAGE) { |
300 | if (n == VECTOR_DATA_STORAGE) |
328 | asm volatile ( |
- | |
329 | "mfdar %0\n" |
- | |
330 | : "=r" (badvaddr) |
301 | badvaddr = istate->dar; |
331 | ); |
- | |
332 | } else |
302 | else |
333 | badvaddr = istate->pc; |
303 | badvaddr = istate->pc; |
334 | 304 | ||
335 | uint32_t physmem; |
305 | uint32_t physmem; |
336 | asm volatile ( |
306 | asm volatile ( |
337 | "mfsprg3 %0\n" |
307 | "mfsprg3 %0\n" |
338 | : "=r" (physmem) |
308 | : "=r" (physmem) |
339 | ); |
309 | ); |
340 | 310 | ||
341 | if ((badvaddr >= PA2KA(0)) && (badvaddr < PA2KA(physmem))) { |
311 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
- | 312 | return false; |
|
- | 313 | ||
- | 314 | uint32_t page = (badvaddr >> 12) & 0xffff; |
|
- | 315 | uint32_t api = (badvaddr >> 22) & 0x3f; |
|
- | 316 | ||
- | 317 | uint32_t vsid; |
|
- | 318 | asm volatile ( |
|
- | 319 | "mfsrin %0, %1\n" |
|
- | 320 | : "=r" (vsid) |
|
- | 321 | : "r" (badvaddr) |
|
- | 322 | ); |
|
- | 323 | ||
- | 324 | uint32_t sdr1; |
|
- | 325 | asm volatile ( |
|
- | 326 | "mfsdr1 %0\n" |
|
- | 327 | : "=r" (sdr1) |
|
- | 328 | ); |
|
- | 329 | phte_t *phte_real = (phte_t *) (sdr1 & 0xffff0000); |
|
- | 330 | ||
- | 331 | /* Primary hash (xor) */ |
|
- | 332 | uint32_t h = 0; |
|
- | 333 | uint32_t hash = vsid ^ page; |
|
- | 334 | uint32_t base = (hash & 0x3ff) << 3; |
|
- | 335 | uint32_t i; |
|
- | 336 | bool found = false; |
|
- | 337 | ||
- | 338 | /* Find colliding PTE in PTEG */ |
|
- | 339 | for (i = 0; i < 8; i++) { |
|
- | 340 | if ((phte_real[base + i].v) |
|
- | 341 | && (phte_real[base + i].vsid == vsid) |
|
- | 342 | && (phte_real[base + i].api == api) |
|
- | 343 | && (phte_real[base + i].h == 0)) { |
|
- | 344 | found = true; |
|
- | 345 | break; |
|
- | 346 | } |
|
- | 347 | } |
|
- | 348 | ||
- | 349 | if (!found) { |
|
- | 350 | /* Find unused PTE in PTEG */ |
|
- | 351 | for (i = 0; i < 8; i++) { |
|
- | 352 | if (!phte_real[base + i].v) { |
|
- | 353 | found = true; |
|
- | 354 | break; |
|
- | 355 | } |
|
- | 356 | } |
|
- | 357 | } |
|
- | 358 | ||
- | 359 | if (!found) { |
|
- | 360 | /* Secondary hash (not) */ |
|
- | 361 | uint32_t base2 = (~hash & 0x3ff) << 3; |
|
- | 362 | ||
- | 363 | /* Find colliding PTE in PTEG */ |
|
- | 364 | for (i = 0; i < 8; i++) { |
|
- | 365 | if ((phte_real[base2 + i].v) |
|
- | 366 | && (phte_real[base2 + i].vsid == vsid) |
|
- | 367 | && (phte_real[base2 + i].api == api) |
|
- | 368 | && (phte_real[base2 + i].h == 1)) { |
|
- | 369 | found = true; |
|
- | 370 | base = base2; |
|
- | 371 | h = 1; |
|
- | 372 | break; |
|
- | 373 | } |
|
- | 374 | } |
|
- | 375 | ||
- | 376 | if (!found) { |
|
- | 377 | /* Find unused PTE in PTEG */ |
|
- | 378 | for (i = 0; i < 8; i++) { |
|
- | 379 | if (!phte_real[base2 + i].v) { |
|
- | 380 | found = true; |
|
- | 381 | base = base2; |
|
- | 382 | h = 1; |
|
- | 383 | break; |
|
- | 384 | } |
|
- | 385 | } |
|
- | 386 | } |
|
- | 387 | ||
- | 388 | if (!found) { |
|
- | 389 | /* Use secondary hash to avoid collisions |
|
- | 390 | with usual PHT refill handler. */ |
|
- | 391 | i = RANDI(seed_real) % 8; |
|
- | 392 | base = base2; |
|
- | 393 | h = 1; |
|
- | 394 | } |
|
- | 395 | } |
|
- | 396 | ||
- | 397 | phte_real[base + i].v = 1; |
|
- | 398 | phte_real[base + i].vsid = vsid; |
|
- | 399 | phte_real[base + i].h = h; |
|
- | 400 | phte_real[base + i].api = api; |
|
342 | pht_real_insert(badvaddr, KA2PA(badvaddr) >> 12); |
401 | phte_real[base + i].rpn = KA2PA(badvaddr) >> 12; |
- | 402 | phte_real[base + i].r = 0; |
|
- | 403 | phte_real[base + i].c = 0; |
|
- | 404 | phte_real[base + i].wimg = 0; |
|
- | 405 | phte_real[base + i].pp = 2; // FIXME |
|
- | 406 | ||
343 | return true; |
407 | return true; |
344 | } |
408 | } |
345 | 409 | ||
- | 410 | ||
- | 411 | /** Process ITLB/DTLB Miss Exception in Real Mode |
|
- | 412 | * |
|
- | 413 | * |
|
- | 414 | */ |
|
- | 415 | void tlb_refill_real(int n, uint32_t tlbmiss, ptehi_t ptehi, ptelo_t ptelo, istate_t *istate) |
|
- | 416 | { |
|
- | 417 | uint32_t badvaddr = tlbmiss & 0xfffffffc; |
|
- | 418 | ||
- | 419 | uint32_t physmem; |
|
- | 420 | asm volatile ( |
|
- | 421 | "mfsprg3 %0\n" |
|
- | 422 | : "=r" (physmem) |
|
- | 423 | ); |
|
- | 424 | ||
- | 425 | if ((badvaddr < PA2KA(0)) || (badvaddr >= PA2KA(physmem))) |
|
346 | return false; |
426 | return; // FIXME |
- | 427 | ||
- | 428 | ptelo.rpn = KA2PA(badvaddr) >> 12; |
|
- | 429 | ptelo.wimg = 0; |
|
- | 430 | ptelo.pp = 2; // FIXME |
|
- | 431 | ||
- | 432 | uint32_t index = 0; |
|
- | 433 | asm volatile ( |
|
- | 434 | "mtspr 981, %0\n" |
|
- | 435 | "mtspr 982, %1\n" |
|
- | 436 | "tlbld %2\n" |
|
- | 437 | "tlbli %2\n" |
|
- | 438 | : "=r" (index) |
|
- | 439 | : "r" (ptehi), |
|
- | 440 | "r" (ptelo) |
|
- | 441 | ); |
|
347 | } |
442 | } |
348 | 443 | ||
349 | 444 | ||
350 | void tlb_arch_init(void) |
445 | void tlb_arch_init(void) |
351 | { |
446 | { |
Line 353... | Line 448... | ||
353 | } |
448 | } |
354 | 449 | ||
355 | 450 | ||
356 | void tlb_invalidate_all(void) |
451 | void tlb_invalidate_all(void) |
357 | { |
452 | { |
- | 453 | uint32_t index; |
|
358 | asm volatile ( |
454 | asm volatile ( |
- | 455 | "li %0, 0\n" |
|
- | 456 | "sync\n" |
|
- | 457 | ||
- | 458 | TLB_FLUSH |
|
- | 459 | TLB_FLUSH |
|
- | 460 | TLB_FLUSH |
|
- | 461 | TLB_FLUSH |
|
- | 462 | TLB_FLUSH |
|
- | 463 | TLB_FLUSH |
|
- | 464 | TLB_FLUSH |
|
- | 465 | TLB_FLUSH |
|
- | 466 | ||
- | 467 | TLB_FLUSH |
|
- | 468 | TLB_FLUSH |
|
- | 469 | TLB_FLUSH |
|
- | 470 | TLB_FLUSH |
|
- | 471 | TLB_FLUSH |
|
- | 472 | TLB_FLUSH |
|
- | 473 | TLB_FLUSH |
|
- | 474 | TLB_FLUSH |
|
- | 475 | ||
- | 476 | TLB_FLUSH |
|
- | 477 | TLB_FLUSH |
|
- | 478 | TLB_FLUSH |
|
- | 479 | TLB_FLUSH |
|
- | 480 | TLB_FLUSH |
|
- | 481 | TLB_FLUSH |
|
- | 482 | TLB_FLUSH |
|
- | 483 | TLB_FLUSH |
|
- | 484 | ||
- | 485 | TLB_FLUSH |
|
- | 486 | TLB_FLUSH |
|
- | 487 | TLB_FLUSH |
|
- | 488 | TLB_FLUSH |
|
- | 489 | TLB_FLUSH |
|
- | 490 | TLB_FLUSH |
|
- | 491 | TLB_FLUSH |
|
- | 492 | TLB_FLUSH |
|
- | 493 | ||
- | 494 | TLB_FLUSH |
|
- | 495 | TLB_FLUSH |
|
- | 496 | TLB_FLUSH |
|
- | 497 | TLB_FLUSH |
|
- | 498 | TLB_FLUSH |
|
- | 499 | TLB_FLUSH |
|
- | 500 | TLB_FLUSH |
|
- | 501 | TLB_FLUSH |
|
- | 502 | ||
- | 503 | TLB_FLUSH |
|
- | 504 | TLB_FLUSH |
|
- | 505 | TLB_FLUSH |
|
- | 506 | TLB_FLUSH |
|
- | 507 | TLB_FLUSH |
|
- | 508 | TLB_FLUSH |
|
- | 509 | TLB_FLUSH |
|
- | 510 | TLB_FLUSH |
|
- | 511 | ||
- | 512 | TLB_FLUSH |
|
- | 513 | TLB_FLUSH |
|
- | 514 | TLB_FLUSH |
|
- | 515 | TLB_FLUSH |
|
- | 516 | TLB_FLUSH |
|
- | 517 | TLB_FLUSH |
|
- | 518 | TLB_FLUSH |
|
- | 519 | TLB_FLUSH |
|
- | 520 | ||
- | 521 | TLB_FLUSH |
|
- | 522 | TLB_FLUSH |
|
- | 523 | TLB_FLUSH |
|
- | 524 | TLB_FLUSH |
|
- | 525 | TLB_FLUSH |
|
- | 526 | TLB_FLUSH |
|
- | 527 | TLB_FLUSH |
|
- | 528 | TLB_FLUSH |
|
- | 529 | ||
359 | "tlbia\n" |
530 | "eieio\n" |
360 | "tlbsync\n" |
531 | "tlbsync\n" |
- | 532 | "sync\n" |
|
- | 533 | : "=r" (index) |
|
361 | ); |
534 | ); |
362 | } |
535 | } |
363 | 536 | ||
364 | 537 | ||
365 | void tlb_invalidate_asid(asid_t asid) |
538 | void tlb_invalidate_asid(asid_t asid) |
Line 371... | Line 544... | ||
371 | ); |
544 | ); |
372 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
545 | phte_t *phte = (phte_t *) PA2KA(sdr1 & 0xffff0000); |
373 | 546 | ||
374 | uint32_t i; |
547 | uint32_t i; |
375 | for (i = 0; i < 8192; i++) { |
548 | for (i = 0; i < 8192; i++) { |
376 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && (phte[i].vsid < ((asid << 4) + 16))) |
549 | if ((phte[i].v) && (phte[i].vsid >= (asid << 4)) && |
- | 550 | (phte[i].vsid < ((asid << 4) + 16))) |
|
377 | phte[i].v = 0; |
551 | phte[i].v = 0; |
378 | } |
552 | } |
379 | tlb_invalidate_all(); |
553 | tlb_invalidate_all(); |
380 | } |
554 | } |
381 | 555 | ||
Line 405... | Line 579... | ||
405 | length <<= 1; \ |
579 | length <<= 1; \ |
406 | tmp >>= 1; \ |
580 | tmp >>= 1; \ |
407 | } \ |
581 | } \ |
408 | } else \ |
582 | } else \ |
409 | length = 0; \ |
583 | length = 0; \ |
410 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, lower & 0xffff0000, length, mask, ((upper >> 1) & 1) ? " supervisor" : "", (upper & 1) ? " user" : ""); |
584 | printf(name ": page=%.*p frame=%.*p length=%d KB (mask=%#x)%s%s\n", \ |
- | 585 | sizeof(upper) * 2, upper & 0xffff0000, sizeof(lower) * 2, \ |
|
- | 586 | lower & 0xffff0000, length, mask, \ |
|
- | 587 | ((upper >> 1) & 1) ? " supervisor" : "", \ |
|
- | 588 | (upper & 1) ? " user" : ""); |
|
411 | 589 | ||
412 | 590 | ||
413 | void tlb_print(void) |
591 | void tlb_print(void) |
414 | { |
592 | { |
415 | uint32_t sr; |
593 | uint32_t sr; |
Line 419... | Line 597... | ||
419 | asm volatile ( |
597 | asm volatile ( |
420 | "mfsrin %0, %1\n" |
598 | "mfsrin %0, %1\n" |
421 | : "=r" (vsid) |
599 | : "=r" (vsid) |
422 | : "r" (sr << 28) |
600 | : "r" (sr << 28) |
423 | ); |
601 | ); |
- | 602 | printf("sr[%02u]: vsid=%.*p (asid=%u)%s%s\n", sr, |
|
424 | printf("vsid[%d]: VSID=%.*p (ASID=%d)%s%s\n", sr, sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, ((vsid >> 30) & 1) ? " supervisor" : "", ((vsid >> 29) & 1) ? " user" : ""); |
603 | sizeof(vsid) * 2, vsid & 0xffffff, (vsid & 0xffffff) >> 4, |
- | 604 | ((vsid >> 30) & 1) ? " supervisor" : "", |
|
- | 605 | ((vsid >> 29) & 1) ? " user" : ""); |
|
425 | } |
606 | } |
426 | 607 | ||
427 | uint32_t upper; |
608 | uint32_t upper; |
428 | uint32_t lower; |
609 | uint32_t lower; |
429 | uint32_t mask; |
610 | uint32_t mask; |