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Line 58... | Line 58... | ||
58 | * Halt the current CPU until interrupt event. |
58 | * Halt the current CPU until interrupt event. |
59 | */ |
59 | */ |
60 | static inline void cpu_halt(void) |
60 | static inline void cpu_halt(void) |
61 | { |
61 | { |
62 | asm volatile ("hlt\n"); |
62 | asm volatile ("hlt\n"); |
63 | }; |
63 | } |
64 | 64 | ||
65 | static inline void cpu_sleep(void) |
65 | static inline void cpu_sleep(void) |
66 | { |
66 | { |
67 | asm volatile ("hlt\n"); |
67 | asm volatile ("hlt\n"); |
68 | }; |
68 | } |
69 | 69 | ||
70 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
70 | #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
71 | { \ |
71 | { \ |
72 | unative_t res; \ |
72 | unative_t res; \ |
73 | asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
73 | asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
Line 77... | Line 77... | ||
77 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
77 | #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
78 | { \ |
78 | { \ |
79 | asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
79 | asm volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
80 | } |
80 | } |
81 | 81 | ||
82 | GEN_READ_REG(cr0); |
82 | GEN_READ_REG(cr0) |
83 | GEN_READ_REG(cr2); |
83 | GEN_READ_REG(cr2) |
84 | GEN_READ_REG(cr3); |
84 | GEN_READ_REG(cr3) |
85 | GEN_WRITE_REG(cr3); |
85 | GEN_WRITE_REG(cr3) |
86 | 86 | ||
87 | GEN_READ_REG(dr0); |
87 | GEN_READ_REG(dr0) |
88 | GEN_READ_REG(dr1); |
88 | GEN_READ_REG(dr1) |
89 | GEN_READ_REG(dr2); |
89 | GEN_READ_REG(dr2) |
90 | GEN_READ_REG(dr3); |
90 | GEN_READ_REG(dr3) |
91 | GEN_READ_REG(dr6); |
91 | GEN_READ_REG(dr6) |
92 | GEN_READ_REG(dr7); |
92 | GEN_READ_REG(dr7) |
93 | 93 | ||
94 | GEN_WRITE_REG(dr0); |
94 | GEN_WRITE_REG(dr0) |
95 | GEN_WRITE_REG(dr1); |
95 | GEN_WRITE_REG(dr1) |
96 | GEN_WRITE_REG(dr2); |
96 | GEN_WRITE_REG(dr2) |
97 | GEN_WRITE_REG(dr3); |
97 | GEN_WRITE_REG(dr3) |
98 | GEN_WRITE_REG(dr6); |
98 | GEN_WRITE_REG(dr6) |
99 | GEN_WRITE_REG(dr7); |
99 | GEN_WRITE_REG(dr7) |
100 | 100 | ||
101 | /** Byte to port |
101 | /** Byte to port |
102 | * |
102 | * |
103 | * Output byte to port |
103 | * Output byte to port |
104 | * |
104 | * |