WebSVN – HelenOS – Diff – /branches/dd/kernel/arch/arm32/src/exception.c



#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <arch/barrier.h>
#include <print.h>
#include <syscall/syscall.h>
 
/** Offset used in calculation of exception handler's relative address.
 *

 
/** Switches to kernel stack and saves all registers there.
 *
 * Temporary exception stack is used to save a few registers
 * before stack switch takes place.
 *
 */
inline static void setup_stack_and_save_regs()
{
    asm volatile (
        "ldr r13, =exc_stack\n"

            "mov r3, r13\n"
            "stmfd r13!, {r2}\n"
            "mov r2, lr\n"
            "stmfd r13!, {r4-r12}\n"
            "mov r1, r13\n"
           
            /* the following two lines are for debugging */
            "mov sp, #0\n"
            "mov lr, #0\n"
            "msr cpsr_c, r0\n"
           

            "stmfd r1!, {r2}\n"
            "stmfd r1!, {r3}\n"
            "mrs r0, spsr\n"
            "stmfd r1!, {r0}\n"
            "mov r13, r1\n"
           
        "2:\n"
    );
}
 
/** Returns from exception mode.

    );
}
 
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception) \
    asm volatile ( \
        "mov r0, %[exc]\n" \
        "mov r1, r13\n" \
        "bl exc_dispatch\n" \
        :: [exc] "i" (exception) \
    );\
 
/** General exception handler.
 *
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.

    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
        PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
    smc_coherence(*vector);
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry(void)
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry(void)
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 

 *
 * CPU is switched to Undefined mode before further interrupt processing
 * because of possible occurence of nested interrupt exception, which
 * would overwrite (and thus spoil) stack pointer.
 */
static void irq_exception_entry(void)
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
   
    switch_to_irq_servicing_mode();

/** Activates use of high exception vectors addresses. */
static void high_vectors(void)
{
    uint32_t control_reg;
   
    asm volatile (
        "mrc p15, 0, %[control_reg], c1, c1"
        : [control_reg] "=r" (control_reg)
    );
   
    /* switch on the high vectors bit */
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile (
        "mcr p15, 0, %[control_reg], c1, c1"
        :: [control_reg] "r" (control_reg)
    );
}
#endif
 
/** Initializes exception handling.
 *

Rev 3022	Rev 4055
Line 38...	Line 38...
38	#include <arch/memstr.h>	38	#include <arch/memstr.h>
39	#include <arch/regutils.h>	39	#include <arch/regutils.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41	#include <arch/machine.h>	41	#include <arch/machine.h>
42	#include <arch/mm/page_fault.h>	42	#include <arch/mm/page_fault.h>
-		43	#include <arch/barrier.h>
43	#include <print.h>	44	#include <print.h>
44	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
45		46
46	/** Offset used in calculation of exception handler's relative address.	47	/** Offset used in calculation of exception handler's relative address.
47	*	48	*
Line 60...	Line 61...
60		61
61	/** Switches to kernel stack and saves all registers there.	62	/** Switches to kernel stack and saves all registers there.
62	*	63	*
63	* Temporary exception stack is used to save a few registers	64	* Temporary exception stack is used to save a few registers
64	* before stack switch takes place.	65	* before stack switch takes place.
-		66	*
65	*/	67	*/
66	inline static void setup_stack_and_save_regs()	68	inline static void setup_stack_and_save_regs()
67	{	69	{
68	asm volatile(	70	asm volatile (
69	"ldr r13, =exc_stack \n"	71	"ldr r13, =exc_stack\n"
Line 97...	Line 99...
97	"mov r3, r13 \n"	99	"mov r3, r13\n"
98	"stmfd r13!, {r2} \n"	100	"stmfd r13!, {r2}\n"
99	"mov r2, lr \n"	101	"mov r2, lr\n"
100	"stmfd r13!, {r4-r12} \n"	102	"stmfd r13!, {r4-r12}\n"
101	"mov r1, r13 \n"	103	"mov r1, r13\n"
-		104
102	/* the following two lines are for debugging */	105	/* the following two lines are for debugging */
103	"mov sp, #0 \n"	106	"mov sp, #0\n"
104	"mov lr, #0 \n"	107	"mov lr, #0\n"
105	"msr cpsr_c, r0 \n"	108	"msr cpsr_c, r0\n"
106		109
Line 110...	Line 113...
110	"stmfd r1!, {r2} \n"	113	"stmfd r1!, {r2}\n"
111	"stmfd r1!, {r3} \n"	114	"stmfd r1!, {r3}\n"
112	"mrs r0, spsr \n"	115	"mrs r0, spsr\n"
113	"stmfd r1!, {r0} \n"	116	"stmfd r1!, {r0}\n"
114	"mov r13, r1 \n"	117	"mov r13, r1\n"
-		118
115	"2:\n"	119	"2:\n"
116	);	120	);
117	}	121	}
118		122
119	/** Returns from exception mode.	123	/** Returns from exception mode.
Line 187...	Line 191...
187	);	191	);
188	}	192	}
189		193
190	/** Calls exception dispatch routine. */	194	/** Calls exception dispatch routine. */
191	#define CALL_EXC_DISPATCH(exception) \	195	#define CALL_EXC_DISPATCH(exception) \
-		196	asm volatile ( \
192	asm("mov r0, %0" : : "i" (exception)); \	197	"mov r0, %[exc]\n" \
193	asm("mov r1, r13"); \	198	"mov r1, r13\n" \
194	asm("bl exc_dispatch");	199	"bl exc_dispatch\n" \
-		200	:: [exc] "i" (exception) \
-		201	);\
195		202
196	/** General exception handler.	203	/** General exception handler.
197	*	204	*
198	* Stores registers, dispatches the exception,	205	* Stores registers, dispatches the exception,
199	* and finally restores registers and returns from exception processing.	206	* and finally restores registers and returns from exception processing.
Line 217...	Line 224...
217	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -	224	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
218	PREFETCH_OFFSET;	225	PREFETCH_OFFSET;
219		226
220	/* make it LDR instruction and store at exception vector */	227	/* make it LDR instruction and store at exception vector */
221	*vector = handler_address_ptr \| LDR_OPCODE;	228	*vector = handler_address_ptr \| LDR_OPCODE;
-		229	smc_coherence(*vector);
222		230
223	/* store handler's address */	231	/* store handler's address */
224	*(vector + EXC_VECTORS) = handler_addr;	232	*(vector + EXC_VECTORS) = handler_addr;
225		233
226	}	234	}
227		235
228	/** Low-level Reset Exception handler. */	236	/** Low-level Reset Exception handler. */
229	static void reset_exception_entry()	237	static void reset_exception_entry(void)
230	{	238	{
231	PROCESS_EXCEPTION(EXC_RESET);	239	PROCESS_EXCEPTION(EXC_RESET);
232	}	240	}
233		241
234	/** Low-level Software Interrupt Exception handler. */	242	/** Low-level Software Interrupt Exception handler. */
235	static void swi_exception_entry()	243	static void swi_exception_entry(void)
236	{	244	{
237	PROCESS_EXCEPTION(EXC_SWI);	245	PROCESS_EXCEPTION(EXC_SWI);
238	}	246	}
239		247
240	/** Low-level Undefined Instruction Exception handler. */	248	/** Low-level Undefined Instruction Exception handler. */
241	static void undef_instr_exception_entry()	249	static void undef_instr_exception_entry(void)
242	{	250	{
243	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	251	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
244	}	252	}
245		253
246	/** Low-level Fast Interrupt Exception handler. */	254	/** Low-level Fast Interrupt Exception handler. */
247	static void fiq_exception_entry()	255	static void fiq_exception_entry(void)
248	{	256	{
249	PROCESS_EXCEPTION(EXC_FIQ);	257	PROCESS_EXCEPTION(EXC_FIQ);
250	}	258	}
251		259
252	/** Low-level Prefetch Abort Exception handler. */	260	/** Low-level Prefetch Abort Exception handler. */
253	static void prefetch_abort_exception_entry()	261	static void prefetch_abort_exception_entry(void)
254	{	262	{
255	asm("sub lr, lr, #4");	263	asm("sub lr, lr, #4");
256	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	264	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
257	}	265	}
258		266
259	/** Low-level Data Abort Exception handler. */	267	/** Low-level Data Abort Exception handler. */
260	static void data_abort_exception_entry()	268	static void data_abort_exception_entry(void)
261	{	269	{
262	asm("sub lr, lr, #8");	270	asm("sub lr, lr, #8");
263	PROCESS_EXCEPTION(EXC_DATA_ABORT);	271	PROCESS_EXCEPTION(EXC_DATA_ABORT);
264	}	272	}
265		273
Line 267...	Line 275...
267	*	275	*
268	* CPU is switched to Undefined mode before further interrupt processing	276	* CPU is switched to Undefined mode before further interrupt processing
269	* because of possible occurence of nested interrupt exception, which	277	* because of possible occurence of nested interrupt exception, which
270	* would overwrite (and thus spoil) stack pointer.	278	* would overwrite (and thus spoil) stack pointer.
271	*/	279	*/
272	static void irq_exception_entry()	280	static void irq_exception_entry(void)
273	{	281	{
274	asm("sub lr, lr, #4");	282	asm("sub lr, lr, #4");
275	setup_stack_and_save_regs();	283	setup_stack_and_save_regs();
276		284
277	switch_to_irq_servicing_mode();	285	switch_to_irq_servicing_mode();
Line 329...	Line 337...
329	/** Activates use of high exception vectors addresses. */	337	/** Activates use of high exception vectors addresses. */
330	static void high_vectors(void)	338	static void high_vectors(void)
331	{	339	{
332	uint32_t control_reg;	340	uint32_t control_reg;
333		341
-		342	asm volatile (
-		343	"mrc p15, 0, %[control_reg], c1, c1"
334	asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));	344	: [control_reg] "=r" (control_reg)
-		345	);
335		346
336	/* switch on the high vectors bit */	347	/* switch on the high vectors bit */
337	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	348	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
338		349
-		350	asm volatile (
-		351	"mcr p15, 0, %[control_reg], c1, c1"
339	asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	352	:: [control_reg] "r" (control_reg)
-		353	);
340	}	354	}
341	#endif	355	#endif
342		356
343	/** Initializes exception handling.	357	/** Initializes exception handling.
344	*	358	*

Subversion Repositories HelenOS

(root)/branches/dd/kernel/arch/arm32/src/exception.c – Rev 3022 → 4055