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/* pte should point into ptl3 */
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/* pte should point into ptl3 */
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#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
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#define PTE_GET_FRAME_ARCH(pte)         ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
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/* pte should point into ptl3 */
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/* pte should point into ptl3 */
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#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
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#define PTE_WRITABLE_ARCH(pte)          ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
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#define PTE_EXECUTABLE_ARCH(pte)            1
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#define PTE_EXECUTABLE_ARCH(pte)        1
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#ifndef __ASM__
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#ifndef __ASM__
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/** Level 0 page table entry. */
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typedef struct {
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    /* 01b for coarse tables, see below for details */
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    unsigned descriptor_type     : 2;
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    unsigned impl_specific       : 3;
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    unsigned domain              : 4;
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    unsigned should_be_zero      : 1;
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    /* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
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     * or large (64KB) pages. ARM also supports fine 2nd level page tables that
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     * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
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     * with 1KB per the coarse table)
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    */
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    unsigned coarse_table_addr   : 22;
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} __attribute__ ((packed)) pte_level0_t;
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/** Level 1 page table entry (small (4KB) pages used) */
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typedef struct {
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    /* 0b10 for small pages */
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    unsigned descriptor_type     : 2;
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    unsigned bufferable          : 1;
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    unsigned cacheable           : 1;
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    /* access permissions for each of 4 subparts of a page
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     * (for each 1KB when small pages used */
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    unsigned access_permission_0 : 2;
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    unsigned access_permission_1 : 2;
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    unsigned access_permission_2 : 2;
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    unsigned access_permission_3 : 2;
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    unsigned frame_base_addr     : 20;
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} __attribute__ ((packed)) pte_level1_t;
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/* Level 1 page tables access permissions */
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/** User mode: no access, privileged mode: no access */
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#define PTE_AP_USER_NO_KERNEL_NO 0
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/** User mode: no access, privileged mode: read/write */
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#define PTE_AP_USER_NO_KERNEL_RW 1
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/** User mode: read only, privileged mode: read/write */
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#define PTE_AP_USER_RO_KERNEL_RW 2
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/** User mode: read/write, privileged mode: read/write */
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#define PTE_AP_USER_RW_KERNEL_RW 3
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/* pte_level0_t and pte_level1_t descriptor_type flags */
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/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
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#define PTE_DESCRIPTOR_NOT_PRESENT  0
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/** pte_level0_t coarse page table flag (used in descriptor_type) */
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#define PTE_DESCRIPTOR_COARSE_TABLE 1
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/** pte_level1_t small page table flag (used in descriptor type) */
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#define PTE_DESCRIPTOR_SMALL_PAGE   2
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/**
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/**
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 * Sets the address of level 0 page table.
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 * Sets the address of level 0 page table.
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 *
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 *
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 * \param pt    pointer to the page table to set
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 * \param pt    pointer to the page table to set
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 */  
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 */  
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static inline void set_ptl0_addr( pte_level0_t* pt)
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static inline void set_ptl0_addr( pte_level0_t* pt)
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{
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{
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    asm volatile (
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    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
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        "mcr p15, 0, %0, c2, c0, 0 \n"
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        :
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        :
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        : "r"(pt)
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        : "r"(pt)
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    );
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    );
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}
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}
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/** Returns level 0 page table entry flags.
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/** Returns level 0 page table entry flags.
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 *
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 *
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 *  \param pt     level 0 page table
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 *  \param pt     level 0 page table