WebSVN – HelenOS-historic – Diff – /uspace/trunk/pci/libpci/i386-ports.c


/*
 *  The PCI Library -- Direct Configuration access via i386 Ports
 *
 *  Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
 *
 *  Modified and ported to HelenOS by Jakub Jermar.
 *
 *  Can be freely distributed and used under the terms of the GNU GPL.
 */
 
#include <unistd.h>
 
#include "internal.h"
 
static inline void outb(u8 b, u16 port)
{
    asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port));
}
 
static inline void outw(u16 w, u16 port)
{
    asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port));
}
 
static inline void outl(u32 l, u16 port)
{
    asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port));
}
 
static inline u8 inb(u16 port)
{
    u8 val;
 
    asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port));
    return val;
}
 
static inline u16 inw(u16 port)
{
    u16 val;
 
    asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port));
    return val;
}
 
static inline u32 inl(u16 port)
{
    u32 val;
 
    asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port));
    return val;
}
 
static void conf12_init(struct pci_access *a)
{
}
 
static void conf12_cleanup(struct pci_access *a UNUSED)
{
}
 
/*
 * Before we decide to use direct hardware access mechanisms, we try to do some
 * trivial checks to ensure it at least _seems_ to be working -- we just test
 * whether bus 00 contains a host bridge (this is similar to checking
 * techniques used in XFree86, but ours should be more reliable since we
 * attempt to make use of direct access hints provided by the PCI BIOS).
 *
 * This should be close to trivial, but it isn't, because there are buggy
 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 */
 
static int intel_sanity_check(struct pci_access *a, struct pci_methods *m)
{
    struct pci_dev d;
 
    a->debug("...sanity check");
    d.bus = 0;
    d.func = 0;
    for (d.dev = 0; d.dev < 32; d.dev++) {
        u16 class, vendor;
 
        if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,
             sizeof(class))
            && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)
            || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))
            || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,
                   sizeof(vendor))
            && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)
            || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {
            a->debug("...outside the Asylum at 0/%02x/0",
                 d.dev);
            return 1;
        }
    }
    a->debug("...insane");
    return 0;
}
 
/*
 *  Configuration type 1
 */
 
#define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
 
static int conf1_detect(struct pci_access *a)
{
    unsigned int tmp;
    int res = 0;
 
    outb(0x01, 0xCFB);
    tmp = inl(0xCF8);
    outl(0x80000000, 0xCF8);
    if (inl(0xCF8) == 0x80000000)
        res = 1;
    outl(tmp, 0xCF8);
    if (res)
        res = intel_sanity_check(a, &pm_intel_conf1);
    return res;
}
 
static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xcfc + (pos & 3);
 
    if (pos >= 256)
        return 0;
 
    outl(0x80000000 | ((d->bus & 0xff) << 16) |
         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
 
    switch (len) {
    case 1:
        buf[0] = inb(addr);
        break;
    case 2:
        ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
        break;
    case 4:
        ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
        break;
    default:
        return pci_generic_block_read(d, pos, buf, len);
    }
    return 1;
}
 
static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xcfc + (pos & 3);
 
    if (pos >= 256)
        return 0;
 
    outl(0x80000000 | ((d->bus & 0xff) << 16) |
         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
 
    switch (len) {
    case 1:
        outb(buf[0], addr);
        break;
    case 2:
        outw(le16_to_cpu(((u16 *) buf)[0]), addr);
        break;
    case 4:
        outl(le32_to_cpu(((u32 *) buf)[0]), addr);
        break;
    default:
        return pci_generic_block_write(d, pos, buf, len);
    }
    return 1;
}
 
/*
 *  Configuration type 2. Obsolete and brain-damaged, but existing.
 */
 
static int conf2_detect(struct pci_access *a)
{
    /* This is ugly and tends to produce false positives. Beware. */
 
    outb(0x00, 0xCFB);
    outb(0x00, 0xCF8);
    outb(0x00, 0xCFA);
    if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
        return intel_sanity_check(a, &pm_intel_conf2);
    else
        return 0;
}
 
static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xc000 | (d->dev << 8) | pos;
 
    if (pos >= 256)
        return 0;
 
    if (d->dev >= 16)
        /* conf2 supports only 16 devices per bus */
        return 0;
    outb((d->func << 1) | 0xf0, 0xcf8);
    outb(d->bus, 0xcfa);
    switch (len) {
    case 1:
        buf[0] = inb(addr);
        break;
    case 2:
        ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
        break;
    case 4:
        ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
        break;
    default:
        outb(0, 0xcf8);
        return pci_generic_block_read(d, pos, buf, len);
    }
    outb(0, 0xcf8);
    return 1;
}
 
static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xc000 | (d->dev << 8) | pos;
 
    if (pos >= 256)
        return 0;
 
    if (d->dev >= 16)
 
        d->access->error("conf2_write: only first 16 devices exist.");
    outb((d->func << 1) | 0xf0, 0xcf8);
    outb(d->bus, 0xcfa);
    switch (len) {
    case 1:
        outb(buf[0], addr);
        break;
    case 2:
        outw(le16_to_cpu(*(u16 *) buf), addr);
        break;
    case 4:
        outl(le32_to_cpu(*(u32 *) buf), addr);
        break;
    default:
        outb(0, 0xcf8);
        return pci_generic_block_write(d, pos, buf, len);
    }
    outb(0, 0xcf8);
    return 1;
}
 
struct pci_methods pm_intel_conf1 = {
    "Intel-conf1",
    NULL,           /* config */
    conf1_detect,
    conf12_init,
    conf12_cleanup,
    pci_generic_scan,
    pci_generic_fill_info,
    conf1_read,
    conf1_write,
    NULL,           /* init_dev */
    NULL            /* cleanup_dev */
};
 
struct pci_methods pm_intel_conf2 = {
    "Intel-conf2",
    NULL,           /* config */
    conf2_detect,
    conf12_init,
    conf12_cleanup,
    pci_generic_scan,
    pci_generic_fill_info,
    conf2_read,
    conf2_write,
    NULL,           /* init_dev */
    NULL            /* cleanup_dev */
};
 

Rev 1302	Rev 1307
1	/*	1	/*
2	* The PCI Library -- Direct Configuration access via i386 Ports	2	* The PCI Library -- Direct Configuration access via i386 Ports
3	*	3	*
4	* Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>	4	* Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
5	*	5	*
6	* Modified and ported to HelenOS by Jakub Jermar.	6	* Modified and ported to HelenOS by Jakub Jermar.
7	*	7	*
8	* Can be freely distributed and used under the terms of the GNU GPL.	8	* Can be freely distributed and used under the terms of the GNU GPL.
9	*/	9	*/
10		10
11	#include <unistd.h>	11	#include <unistd.h>
12		12
13	#include "internal.h"	13	#include "internal.h"
14		14
15	static inline void outb(u8 b, u16 port)	15	static inline void outb(u8 b, u16 port)
16	{	16	{
17	asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port));	17	asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port));
18	}	18	}
19		19
20	static inline void outw(u16 w, u16 port)	20	static inline void outw(u16 w, u16 port)
21	{	21	{
22	asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port));	22	asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port));
23	}	23	}
24		24
25	static inline void outl(u32 l, u16 port)	25	static inline void outl(u32 l, u16 port)
26	{	26	{
27	asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port));	27	asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port));
28	}	28	}
29		29
30	static inline u8 inb(u16 port)	30	static inline u8 inb(u16 port)
31	{	31	{
32	u8 val;	32	u8 val;
33		33
34	asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port));	34	asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port));
35	return val;	35	return val;
36	}	36	}
37		37
38	static inline u16 inw(u16 port)	38	static inline u16 inw(u16 port)
39	{	39	{
40	u16 val;	40	u16 val;
41		41
42	asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port));	42	asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port));
43	return val;	43	return val;
44	}	44	}
45		45
46	static inline u32 inl(u16 port)	46	static inline u32 inl(u16 port)
47	{	47	{
48	u32 val;	48	u32 val;
49		49
50	asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port));	50	asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port));
51	return val;	51	return val;
52	}	52	}
53		53
54	static void conf12_init(struct pci_access *a)	54	static void conf12_init(struct pci_access *a)
55	{	55	{
56	}	56	}
57		57
58	static void conf12_cleanup(struct pci_access *a UNUSED)	58	static void conf12_cleanup(struct pci_access *a UNUSED)
59	{	59	{
60	}	60	}
61		61
62	/*	62	/*
63	* Before we decide to use direct hardware access mechanisms, we try to do some	63	* Before we decide to use direct hardware access mechanisms, we try to do some
64	* trivial checks to ensure it at least _seems_ to be working -- we just test	64	* trivial checks to ensure it at least _seems_ to be working -- we just test
65	* whether bus 00 contains a host bridge (this is similar to checking	65	* whether bus 00 contains a host bridge (this is similar to checking
66	* techniques used in XFree86, but ours should be more reliable since we	66	* techniques used in XFree86, but ours should be more reliable since we
67	* attempt to make use of direct access hints provided by the PCI BIOS).	67	* attempt to make use of direct access hints provided by the PCI BIOS).
68	*	68	*
69	* This should be close to trivial, but it isn't, because there are buggy	69	* This should be close to trivial, but it isn't, because there are buggy
70	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.	70	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
71	*/	71	*/
72		72
73	static int intel_sanity_check(struct pci_access a, struct pci_methods m)	73	static int intel_sanity_check(struct pci_access a, struct pci_methods m)
74	{	74	{
75	struct pci_dev d;	75	struct pci_dev d;
76		76
77	a->debug("...sanity check");	77	a->debug("...sanity check");
78	d.bus = 0;	78	d.bus = 0;
79	d.func = 0;	79	d.func = 0;
80	for (d.dev = 0; d.dev < 32; d.dev++) {	80	for (d.dev = 0; d.dev < 32; d.dev++) {
81	u16 class, vendor;	81	u16 class, vendor;
82	if (m->	-
83	read(&d, PCI_CLASS_DEVICE, (byte *) & class,	82	if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,
84	sizeof(class))	83	sizeof(class))
85	&& (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)	84	&& (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)
86	\|\| class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))	85	\|\| class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))
87	\|\| m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,	86	\|\| m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,
88	sizeof(vendor))	87	sizeof(vendor))
89	&& (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)	88	&& (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)
90	\|\| vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {	89	\|\| vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {
91	a->debug("...outside the Asylum at 0/%02x/0",	90	a->debug("...outside the Asylum at 0/%02x/0",
92	d.dev);	91	d.dev);
93	return 1;	92	return 1;
94	}	93	}
95	}	94	}
96	a->debug("...insane");	95	a->debug("...insane");
97	return 0;	96	return 0;
98	}	97	}
99		98
100	/*	99	/*
101	* Configuration type 1	100	* Configuration type 1
102	*/	101	*/
103		102
104	#define CONFIG_CMD(bus, device_fn, where) (0x80000000 \| (bus << 16) \| (device_fn << 8) \| (where & ~3))	103	#define CONFIG_CMD(bus, device_fn, where) (0x80000000 \| (bus << 16) \| (device_fn << 8) \| (where & ~3))
105		104
106	static int conf1_detect(struct pci_access *a)	105	static int conf1_detect(struct pci_access *a)
107	{	106	{
108	unsigned int tmp;	107	unsigned int tmp;
109	int res = 0;	108	int res = 0;
110		109
111	outb(0x01, 0xCFB);	110	outb(0x01, 0xCFB);
112	tmp = inl(0xCF8);	111	tmp = inl(0xCF8);
113	outl(0x80000000, 0xCF8);	112	outl(0x80000000, 0xCF8);
114	if (inl(0xCF8) == 0x80000000)	113	if (inl(0xCF8) == 0x80000000)
115	res = 1;	114	res = 1;
116	outl(tmp, 0xCF8);	115	outl(tmp, 0xCF8);
117	if (res)	116	if (res)
118	res = intel_sanity_check(a, &pm_intel_conf1);	117	res = intel_sanity_check(a, &pm_intel_conf1);
119	return res;	118	return res;
120	}	119	}
121		120
122	static int conf1_read(struct pci_dev d, int pos, byte buf, int len)	121	static int conf1_read(struct pci_dev d, int pos, byte buf, int len)
123	{	122	{
124	int addr = 0xcfc + (pos & 3);	123	int addr = 0xcfc + (pos & 3);
125		124
126	if (pos >= 256)	125	if (pos >= 256)
127	return 0;	126	return 0;
128		127
129	outl(0x80000000 \| ((d->bus & 0xff) << 16) \|	128	outl(0x80000000 \| ((d->bus & 0xff) << 16) \|
130	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3), 0xcf8);	129	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3), 0xcf8);
131		130
132	switch (len) {	131	switch (len) {
133	case 1:	132	case 1:
134	buf[0] = inb(addr);	133	buf[0] = inb(addr);
135	break;	134	break;
136	case 2:	135	case 2:
137	((u16 *) buf)[0] = cpu_to_le16(inw(addr));	136	((u16 *) buf)[0] = cpu_to_le16(inw(addr));
138	break;	137	break;
139	case 4:	138	case 4:
140	((u32 *) buf)[0] = cpu_to_le32(inl(addr));	139	((u32 *) buf)[0] = cpu_to_le32(inl(addr));
141	break;	140	break;
142	default:	141	default:
143	return pci_generic_block_read(d, pos, buf, len);	142	return pci_generic_block_read(d, pos, buf, len);
144	}	143	}
145	return 1;	144	return 1;
146	}	145	}
147		146
148	static int conf1_write(struct pci_dev d, int pos, byte buf, int len)	147	static int conf1_write(struct pci_dev d, int pos, byte buf, int len)
149	{	148	{
150	int addr = 0xcfc + (pos & 3);	149	int addr = 0xcfc + (pos & 3);
151		150
152	if (pos >= 256)	151	if (pos >= 256)
153	return 0;	152	return 0;
154		153
155	outl(0x80000000 \| ((d->bus & 0xff) << 16) \|	154	outl(0x80000000 \| ((d->bus & 0xff) << 16) \|
156	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3), 0xcf8);	155	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3), 0xcf8);
157		156
158	switch (len) {	157	switch (len) {
159	case 1:	158	case 1:
160	outb(buf[0], addr);	159	outb(buf[0], addr);
161	break;	160	break;
162	case 2:	161	case 2:
163	outw(le16_to_cpu(((u16 *) buf)[0]), addr);	162	outw(le16_to_cpu(((u16 *) buf)[0]), addr);
164	break;	163	break;
165	case 4:	164	case 4:
166	outl(le32_to_cpu(((u32 *) buf)[0]), addr);	165	outl(le32_to_cpu(((u32 *) buf)[0]), addr);
167	break;	166	break;
168	default:	167	default:
169	return pci_generic_block_write(d, pos, buf, len);	168	return pci_generic_block_write(d, pos, buf, len);
170	}	169	}
171	return 1;	170	return 1;
172	}	171	}
173		172
174	/*	173	/*
175	* Configuration type 2. Obsolete and brain-damaged, but existing.	174	* Configuration type 2. Obsolete and brain-damaged, but existing.
176	*/	175	*/
177		176
178	static int conf2_detect(struct pci_access *a)	177	static int conf2_detect(struct pci_access *a)
179	{	178	{
180	/* This is ugly and tends to produce false positives. Beware. */	179	/* This is ugly and tends to produce false positives. Beware. */
181		-
182	outb(0x00, 0xCFB);	180	outb(0x00, 0xCFB);
183	outb(0x00, 0xCF8);	181	outb(0x00, 0xCF8);
184	outb(0x00, 0xCFA);	182	outb(0x00, 0xCFA);
185	if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)	183	if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
186	return intel_sanity_check(a, &pm_intel_conf2);	184	return intel_sanity_check(a, &pm_intel_conf2);
187	else	185	else
188	return 0;	186	return 0;
189	}	187	}
190		188
191	static int conf2_read(struct pci_dev d, int pos, byte buf, int len)	189	static int conf2_read(struct pci_dev d, int pos, byte buf, int len)
192	{	190	{
193	int addr = 0xc000 \| (d->dev << 8) \| pos;	191	int addr = 0xc000 \| (d->dev << 8) \| pos;
194		192
195	if (pos >= 256)	193	if (pos >= 256)
196	return 0;	194	return 0;
197		195
198	if (d->dev >= 16)	196	if (d->dev >= 16)
199	/* conf2 supports only 16 devices per bus */	197	/* conf2 supports only 16 devices per bus */
200	return 0;	198	return 0;
201	outb((d->func << 1) \| 0xf0, 0xcf8);	199	outb((d->func << 1) \| 0xf0, 0xcf8);
202	outb(d->bus, 0xcfa);	200	outb(d->bus, 0xcfa);
203	switch (len) {	201	switch (len) {
204	case 1:	202	case 1:
205	buf[0] = inb(addr);	203	buf[0] = inb(addr);
206	break;	204	break;
207	case 2:	205	case 2:
208	((u16 *) buf)[0] = cpu_to_le16(inw(addr));	206	((u16 *) buf)[0] = cpu_to_le16(inw(addr));
209	break;	207	break;
210	case 4:	208	case 4:
211	((u32 *) buf)[0] = cpu_to_le32(inl(addr));	209	((u32 *) buf)[0] = cpu_to_le32(inl(addr));
212	break;	210	break;
213	default:	211	default:
214	outb(0, 0xcf8);	212	outb(0, 0xcf8);
215	return pci_generic_block_read(d, pos, buf, len);	213	return pci_generic_block_read(d, pos, buf, len);
216	}	214	}
217	outb(0, 0xcf8);	215	outb(0, 0xcf8);
218	return 1;	216	return 1;
219	}	217	}
220		218
221	static int conf2_write(struct pci_dev d, int pos, byte buf, int len)	219	static int conf2_write(struct pci_dev d, int pos, byte buf, int len)
222	{	220	{
223	int addr = 0xc000 \| (d->dev << 8) \| pos;	221	int addr = 0xc000 \| (d->dev << 8) \| pos;
224		222
225	if (pos >= 256)	223	if (pos >= 256)
226	return 0;	224	return 0;
227		225
228	if (d->dev >= 16)	226	if (d->dev >= 16)
229	d->access->	-
230	error("conf2_write: only first 16 devices exist.");	227	d->access->error("conf2_write: only first 16 devices exist.");
231	outb((d->func << 1) \| 0xf0, 0xcf8);	228	outb((d->func << 1) \| 0xf0, 0xcf8);
232	outb(d->bus, 0xcfa);	229	outb(d->bus, 0xcfa);
233	switch (len) {	230	switch (len) {
234	case 1:	231	case 1:
235	outb(buf[0], addr);	232	outb(buf[0], addr);
236	break;	233	break;
237	case 2:	234	case 2:
238	outw(le16_to_cpu((u16 ) buf), addr);	235	outw(le16_to_cpu((u16 ) buf), addr);
239	break;	236	break;
240	case 4:	237	case 4:
241	outl(le32_to_cpu((u32 ) buf), addr);	238	outl(le32_to_cpu((u32 ) buf), addr);
242	break;	239	break;
243	default:	240	default:
244	outb(0, 0xcf8);	241	outb(0, 0xcf8);
245	return pci_generic_block_write(d, pos, buf, len);	242	return pci_generic_block_write(d, pos, buf, len);
246	}	243	}
247	outb(0, 0xcf8);	244	outb(0, 0xcf8);
248	return 1;	245	return 1;
249	}	246	}
250		247
251	struct pci_methods pm_intel_conf1 = {	248	struct pci_methods pm_intel_conf1 = {
252	"Intel-conf1",	249	"Intel-conf1",
253	NULL, /* config */	250	NULL, /* config */
254	conf1_detect,	251	conf1_detect,
255	conf12_init,	252	conf12_init,
256	conf12_cleanup,	253	conf12_cleanup,
257	pci_generic_scan,	254	pci_generic_scan,
258	pci_generic_fill_info,	255	pci_generic_fill_info,
259	conf1_read,	256	conf1_read,
260	conf1_write,	257	conf1_write,
261	NULL, /* init_dev */	258	NULL, /* init_dev */
262	NULL /* cleanup_dev */	259	NULL /* cleanup_dev */
263	};	260	};
264		261
265	struct pci_methods pm_intel_conf2 = {	262	struct pci_methods pm_intel_conf2 = {
266	"Intel-conf2",	263	"Intel-conf2",
267	NULL, /* config */	264	NULL, /* config */
268	conf2_detect,	265	conf2_detect,
269	conf12_init,	266	conf12_init,
270	conf12_cleanup,	267	conf12_cleanup,
271	pci_generic_scan,	268	pci_generic_scan,
272	pci_generic_fill_info,	269	pci_generic_fill_info,
273	conf2_read,	270	conf2_read,
274	conf2_write,	271	conf2_write,
275	NULL, /* init_dev */	272	NULL, /* init_dev */
276	NULL /* cleanup_dev */	273	NULL /* cleanup_dev */
277	};	274	};
278		275

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(root)/uspace/trunk/pci/libpci/i386-ports.c – Rev 1302 → 1307