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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** |
29 | /** |
30 | * @file tlb.c |
30 | * @file tlb.c |
31 | * @brief Generic TLB shootdown algorithm. |
31 | * @brief Generic TLB shootdown algorithm. |
- | 32 | * |
|
- | 33 | * The algorithm implemented here is based on the CMU TLB shootdown |
|
- | 34 | * algorithm and is further simplified (e.g. all CPUs receive all TLB |
|
- | 35 | * shootdown messages). |
|
32 | */ |
36 | */ |
33 | 37 | ||
34 | #include <mm/tlb.h> |
38 | #include <mm/tlb.h> |
35 | #include <mm/asid.h> |
39 | #include <mm/asid.h> |
36 | #include <arch/mm/tlb.h> |
40 | #include <arch/mm/tlb.h> |
37 | #include <smp/ipi.h> |
41 | #include <smp/ipi.h> |
38 | #include <synch/spinlock.h> |
42 | #include <synch/spinlock.h> |
39 | #include <typedefs.h> |
43 | #include <typedefs.h> |
40 | #include <atomic.h> |
44 | #include <atomic.h> |
41 | #include <arch/interrupt.h> |
45 | #include <arch/interrupt.h> |
42 | #include <config.h> |
46 | #include <config.h> |
43 | #include <arch.h> |
47 | #include <arch.h> |
44 | #include <panic.h> |
48 | #include <panic.h> |
45 | #include <debug.h> |
49 | #include <debug.h> |
46 | 50 | ||
47 | /** |
51 | /** |
48 | * This lock is used for synchronisation between sender and |
52 | * This lock is used for synchronisation between sender and |
49 | * recipients of TLB shootdown message. It must be acquired |
53 | * recipients of TLB shootdown message. It must be acquired |
50 | * before CPU structure lock. |
54 | * before CPU structure lock. |
51 | */ |
55 | */ |
52 | SPINLOCK_INITIALIZE(tlblock); |
56 | SPINLOCK_INITIALIZE(tlblock); |
53 | 57 | ||
54 | void tlb_init(void) |
58 | void tlb_init(void) |
55 | { |
59 | { |
56 | tlb_arch_init(); |
60 | tlb_arch_init(); |
57 | } |
61 | } |
58 | 62 | ||
59 | #ifdef CONFIG_SMP |
63 | #ifdef CONFIG_SMP |
60 | 64 | ||
61 | /** Send TLB shootdown message. |
65 | /** Send TLB shootdown message. |
62 | * |
66 | * |
63 | * This function attempts to deliver TLB shootdown message |
67 | * This function attempts to deliver TLB shootdown message |
64 | * to all other processors. |
68 | * to all other processors. |
65 | * |
69 | * |
66 | * This function must be called with interrupts disabled. |
70 | * This function must be called with interrupts disabled. |
67 | * |
71 | * |
68 | * @param type Type describing scope of shootdown. |
72 | * @param type Type describing scope of shootdown. |
69 | * @param asid Address space, if required by type. |
73 | * @param asid Address space, if required by type. |
70 | * @param page Virtual page address, if required by type. |
74 | * @param page Virtual page address, if required by type. |
71 | * @param count Number of pages, if required by type. |
75 | * @param count Number of pages, if required by type. |
72 | */ |
76 | */ |
73 | void tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid, __address page, count_t count) |
77 | void tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid, __address page, count_t count) |
74 | { |
78 | { |
75 | int i; |
79 | int i; |
76 | 80 | ||
77 | CPU->tlb_active = 0; |
81 | CPU->tlb_active = 0; |
78 | spinlock_lock(&tlblock); |
82 | spinlock_lock(&tlblock); |
79 | 83 | ||
80 | for (i = 0; i < config.cpu_count; i++) { |
84 | for (i = 0; i < config.cpu_count; i++) { |
81 | cpu_t *cpu; |
85 | cpu_t *cpu; |
82 | 86 | ||
83 | if (i == CPU->id) |
87 | if (i == CPU->id) |
84 | continue; |
88 | continue; |
85 | 89 | ||
86 | cpu = &cpus[i]; |
90 | cpu = &cpus[i]; |
87 | spinlock_lock(&cpu->lock); |
91 | spinlock_lock(&cpu->lock); |
88 | if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) { |
92 | if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) { |
89 | /* |
93 | /* |
90 | * The message queue is full. |
94 | * The message queue is full. |
91 | * Erase the queue and store one TLB_INVL_ALL message. |
95 | * Erase the queue and store one TLB_INVL_ALL message. |
92 | */ |
96 | */ |
93 | cpu->tlb_messages_count = 1; |
97 | cpu->tlb_messages_count = 1; |
94 | cpu->tlb_messages[0].type = TLB_INVL_ALL; |
98 | cpu->tlb_messages[0].type = TLB_INVL_ALL; |
95 | cpu->tlb_messages[0].asid = ASID_INVALID; |
99 | cpu->tlb_messages[0].asid = ASID_INVALID; |
96 | cpu->tlb_messages[0].page = 0; |
100 | cpu->tlb_messages[0].page = 0; |
97 | cpu->tlb_messages[0].count = 0; |
101 | cpu->tlb_messages[0].count = 0; |
98 | } else { |
102 | } else { |
99 | /* |
103 | /* |
100 | * Enqueue the message. |
104 | * Enqueue the message. |
101 | */ |
105 | */ |
102 | cpu->tlb_messages[cpu->tlb_messages_count].type = type; |
106 | cpu->tlb_messages[cpu->tlb_messages_count].type = type; |
103 | cpu->tlb_messages[cpu->tlb_messages_count].asid = asid; |
107 | cpu->tlb_messages[cpu->tlb_messages_count].asid = asid; |
104 | cpu->tlb_messages[cpu->tlb_messages_count].page = page; |
108 | cpu->tlb_messages[cpu->tlb_messages_count].page = page; |
105 | cpu->tlb_messages[cpu->tlb_messages_count].count = count; |
109 | cpu->tlb_messages[cpu->tlb_messages_count].count = count; |
106 | cpu->tlb_messages_count++; |
110 | cpu->tlb_messages_count++; |
107 | } |
111 | } |
108 | spinlock_unlock(&cpu->lock); |
112 | spinlock_unlock(&cpu->lock); |
109 | } |
113 | } |
110 | 114 | ||
111 | tlb_shootdown_ipi_send(); |
115 | tlb_shootdown_ipi_send(); |
112 | 116 | ||
113 | busy_wait: |
117 | busy_wait: |
114 | for (i = 0; i < config.cpu_count; i++) |
118 | for (i = 0; i < config.cpu_count; i++) |
115 | if (cpus[i].tlb_active) |
119 | if (cpus[i].tlb_active) |
116 | goto busy_wait; |
120 | goto busy_wait; |
117 | } |
121 | } |
118 | 122 | ||
119 | /** Finish TLB shootdown sequence. */ |
123 | /** Finish TLB shootdown sequence. */ |
120 | void tlb_shootdown_finalize(void) |
124 | void tlb_shootdown_finalize(void) |
121 | { |
125 | { |
122 | spinlock_unlock(&tlblock); |
126 | spinlock_unlock(&tlblock); |
123 | CPU->tlb_active = 1; |
127 | CPU->tlb_active = 1; |
124 | } |
128 | } |
125 | 129 | ||
126 | void tlb_shootdown_ipi_send(void) |
130 | void tlb_shootdown_ipi_send(void) |
127 | { |
131 | { |
128 | ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI); |
132 | ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI); |
129 | } |
133 | } |
130 | 134 | ||
131 | /** Receive TLB shootdown message. */ |
135 | /** Receive TLB shootdown message. */ |
132 | void tlb_shootdown_ipi_recv(void) |
136 | void tlb_shootdown_ipi_recv(void) |
133 | { |
137 | { |
134 | tlb_invalidate_type_t type; |
138 | tlb_invalidate_type_t type; |
135 | asid_t asid; |
139 | asid_t asid; |
136 | __address page; |
140 | __address page; |
137 | count_t count; |
141 | count_t count; |
138 | int i; |
142 | int i; |
139 | 143 | ||
140 | ASSERT(CPU); |
144 | ASSERT(CPU); |
141 | 145 | ||
142 | CPU->tlb_active = 0; |
146 | CPU->tlb_active = 0; |
143 | spinlock_lock(&tlblock); |
147 | spinlock_lock(&tlblock); |
144 | spinlock_unlock(&tlblock); |
148 | spinlock_unlock(&tlblock); |
145 | 149 | ||
146 | spinlock_lock(&CPU->lock); |
150 | spinlock_lock(&CPU->lock); |
147 | ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN); |
151 | ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN); |
148 | 152 | ||
149 | for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) { |
153 | for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) { |
150 | type = CPU->tlb_messages[i].type; |
154 | type = CPU->tlb_messages[i].type; |
151 | asid = CPU->tlb_messages[i].asid; |
155 | asid = CPU->tlb_messages[i].asid; |
152 | page = CPU->tlb_messages[i].page; |
156 | page = CPU->tlb_messages[i].page; |
153 | count = CPU->tlb_messages[i].count; |
157 | count = CPU->tlb_messages[i].count; |
154 | 158 | ||
155 | switch (type) { |
159 | switch (type) { |
156 | case TLB_INVL_ALL: |
160 | case TLB_INVL_ALL: |
157 | tlb_invalidate_all(); |
161 | tlb_invalidate_all(); |
158 | break; |
162 | break; |
159 | case TLB_INVL_ASID: |
163 | case TLB_INVL_ASID: |
160 | tlb_invalidate_asid(asid); |
164 | tlb_invalidate_asid(asid); |
161 | break; |
165 | break; |
162 | case TLB_INVL_PAGES: |
166 | case TLB_INVL_PAGES: |
163 | ASSERT(count); |
167 | ASSERT(count); |
164 | tlb_invalidate_pages(asid, page, count); |
168 | tlb_invalidate_pages(asid, page, count); |
165 | break; |
169 | break; |
166 | default: |
170 | default: |
167 | panic("unknown type (%d)\n", type); |
171 | panic("unknown type (%d)\n", type); |
168 | break; |
172 | break; |
169 | } |
173 | } |
170 | if (type == TLB_INVL_ALL) |
174 | if (type == TLB_INVL_ALL) |
171 | break; |
175 | break; |
172 | } |
176 | } |
173 | 177 | ||
174 | spinlock_unlock(&CPU->lock); |
178 | spinlock_unlock(&CPU->lock); |
175 | CPU->tlb_active = 1; |
179 | CPU->tlb_active = 1; |
176 | } |
180 | } |
177 | 181 | ||
178 | #endif /* CONFIG_SMP */ |
182 | #endif /* CONFIG_SMP */ |
179 | 183 |