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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #include <mm/tlb.h> |
29 | #include <mm/tlb.h> |
30 | #include <mm/asid.h> |
30 | #include <mm/asid.h> |
31 | #include <arch/mm/tlb.h> |
31 | #include <arch/mm/tlb.h> |
32 | #include <smp/ipi.h> |
32 | #include <smp/ipi.h> |
33 | #include <synch/spinlock.h> |
33 | #include <synch/spinlock.h> |
34 | #include <typedefs.h> |
34 | #include <typedefs.h> |
35 | #include <arch/atomic.h> |
35 | #include <arch/atomic.h> |
36 | #include <arch/interrupt.h> |
36 | #include <arch/interrupt.h> |
37 | #include <config.h> |
37 | #include <config.h> |
38 | #include <arch.h> |
38 | #include <arch.h> |
39 | #include <panic.h> |
39 | #include <panic.h> |
40 | #include <debug.h> |
40 | #include <debug.h> |
41 | 41 | ||
42 | /** |
42 | /** |
43 | * This lock is used for synchronisation between sender and |
43 | * This lock is used for synchronisation between sender and |
44 | * recipients of TLB shootdown message. It must be acquired |
44 | * recipients of TLB shootdown message. It must be acquired |
45 | * before CPU structure lock. |
45 | * before CPU structure lock. |
46 | */ |
46 | */ |
47 | SPINLOCK_INITIALIZE(tlblock); |
47 | SPINLOCK_INITIALIZE(tlblock); |
48 | 48 | ||
49 | void tlb_init(void) |
49 | void tlb_init(void) |
50 | { |
50 | { |
51 | tlb_arch_init(); |
51 | tlb_arch_init(); |
52 | } |
52 | } |
53 | 53 | ||
54 | #ifdef CONFIG_SMP |
54 | #ifdef CONFIG_SMP |
55 | 55 | ||
56 | /** Send TLB shootdown message. |
56 | /** Send TLB shootdown message. |
57 | * |
57 | * |
58 | * This function attempts to deliver TLB shootdown message |
58 | * This function attempts to deliver TLB shootdown message |
59 | * to all other processors. |
59 | * to all other processors. |
60 | * |
60 | * |
61 | * This function must be called with interrupts disabled. |
61 | * This function must be called with interrupts disabled. |
62 | * |
62 | * |
63 | * @param type Type describing scope of shootdown. |
63 | * @param type Type describing scope of shootdown. |
64 | * @param asid Address space, if required by type. |
64 | * @param asid Address space, if required by type. |
65 | * @param page Virtual page address, if required by type. |
65 | * @param page Virtual page address, if required by type. |
66 | * @param count Number of pages, if required by type. |
66 | * @param count Number of pages, if required by type. |
67 | */ |
67 | */ |
68 | void tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid, __address page, count_t count) |
68 | void tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid, __address page, count_t count) |
69 | { |
69 | { |
70 | int i; |
70 | int i; |
71 | 71 | ||
72 | CPU->tlb_active = 0; |
72 | CPU->tlb_active = 0; |
73 | spinlock_lock(&tlblock); |
73 | spinlock_lock(&tlblock); |
74 | 74 | ||
75 | for (i = 0; i < config.cpu_count; i++) { |
75 | for (i = 0; i < config.cpu_count; i++) { |
76 | cpu_t *cpu; |
76 | cpu_t *cpu; |
77 | 77 | ||
78 | if (i == CPU->id) |
78 | if (i == CPU->id) |
79 | continue; |
79 | continue; |
80 | 80 | ||
81 | cpu = &cpus[i]; |
81 | cpu = &cpus[i]; |
82 | spinlock_lock(&cpu->lock); |
82 | spinlock_lock(&cpu->lock); |
83 | if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) { |
83 | if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) { |
84 | /* |
84 | /* |
85 | * The message queue is full. |
85 | * The message queue is full. |
86 | * Erase the queue and store one TLB_INVL_ALL message. |
86 | * Erase the queue and store one TLB_INVL_ALL message. |
87 | */ |
87 | */ |
88 | cpu->tlb_messages_count = 1; |
88 | cpu->tlb_messages_count = 1; |
89 | cpu->tlb_messages[0].type = TLB_INVL_ALL; |
89 | cpu->tlb_messages[0].type = TLB_INVL_ALL; |
90 | cpu->tlb_messages[0].asid = ASID_INVALID; |
90 | cpu->tlb_messages[0].asid = ASID_INVALID; |
91 | cpu->tlb_messages[0].page = 0; |
91 | cpu->tlb_messages[0].page = 0; |
92 | cpu->tlb_messages[0].count = 0; |
92 | cpu->tlb_messages[0].count = 0; |
93 | } else { |
93 | } else { |
94 | /* |
94 | /* |
95 | * Enqueue the message. |
95 | * Enqueue the message. |
96 | */ |
96 | */ |
97 | cpu->tlb_messages[cpu->tlb_messages_count].type = type; |
97 | cpu->tlb_messages[cpu->tlb_messages_count].type = type; |
98 | cpu->tlb_messages[cpu->tlb_messages_count].asid = asid; |
98 | cpu->tlb_messages[cpu->tlb_messages_count].asid = asid; |
99 | cpu->tlb_messages[cpu->tlb_messages_count].page = page; |
99 | cpu->tlb_messages[cpu->tlb_messages_count].page = page; |
100 | cpu->tlb_messages[cpu->tlb_messages_count].count = count; |
100 | cpu->tlb_messages[cpu->tlb_messages_count].count = count; |
101 | cpu->tlb_messages_count++; |
101 | cpu->tlb_messages_count++; |
102 | } |
102 | } |
103 | spinlock_unlock(&cpu->lock); |
103 | spinlock_unlock(&cpu->lock); |
104 | } |
104 | } |
105 | 105 | ||
106 | tlb_shootdown_ipi_send(); |
106 | tlb_shootdown_ipi_send(); |
107 | 107 | ||
108 | busy_wait: |
108 | busy_wait: |
109 | for (i = 0; i < config.cpu_count; i++) |
109 | for (i = 0; i < config.cpu_count; i++) |
110 | if (cpus[i].tlb_active) |
110 | if (cpus[i].tlb_active) |
111 | goto busy_wait; |
111 | goto busy_wait; |
112 | } |
112 | } |
113 | 113 | ||
114 | /** Finish TLB shootdown sequence. */ |
114 | /** Finish TLB shootdown sequence. */ |
115 | void tlb_shootdown_finalize(void) |
115 | void tlb_shootdown_finalize(void) |
116 | { |
116 | { |
117 | spinlock_unlock(&tlblock); |
117 | spinlock_unlock(&tlblock); |
118 | CPU->tlb_active = 1; |
118 | CPU->tlb_active = 1; |
119 | } |
119 | } |
120 | 120 | ||
121 | void tlb_shootdown_ipi_send(void) |
121 | void tlb_shootdown_ipi_send(void) |
122 | { |
122 | { |
123 | ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI); |
123 | ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI); |
124 | } |
124 | } |
125 | 125 | ||
126 | /** Receive TLB shootdown message. */ |
126 | /** Receive TLB shootdown message. */ |
127 | void tlb_shootdown_ipi_recv(void) |
127 | void tlb_shootdown_ipi_recv(void) |
128 | { |
128 | { |
129 | tlb_invalidate_type_t type; |
129 | tlb_invalidate_type_t type; |
130 | asid_t asid; |
130 | asid_t asid; |
131 | __address page; |
131 | __address page; |
132 | count_t count; |
132 | count_t count; |
133 | int i; |
133 | int i; |
134 | 134 | ||
- | 135 | ASSERT(CPU); |
|
- | 136 | ||
135 | CPU->tlb_active = 0; |
137 | CPU->tlb_active = 0; |
136 | spinlock_lock(&tlblock); |
138 | spinlock_lock(&tlblock); |
137 | spinlock_unlock(&tlblock); |
139 | spinlock_unlock(&tlblock); |
138 | 140 | ||
139 | spinlock_lock(&CPU->lock); |
141 | spinlock_lock(&CPU->lock); |
140 | ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN); |
142 | ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN); |
141 | 143 | ||
142 | for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) { |
144 | for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) { |
143 | type = CPU->tlb_messages[i].type; |
145 | type = CPU->tlb_messages[i].type; |
144 | asid = CPU->tlb_messages[i].asid; |
146 | asid = CPU->tlb_messages[i].asid; |
145 | page = CPU->tlb_messages[i].page; |
147 | page = CPU->tlb_messages[i].page; |
146 | count = CPU->tlb_messages[i].count; |
148 | count = CPU->tlb_messages[i].count; |
147 | 149 | ||
148 | switch (type) { |
150 | switch (type) { |
149 | case TLB_INVL_ALL: |
151 | case TLB_INVL_ALL: |
150 | tlb_invalidate_all(); |
152 | tlb_invalidate_all(); |
151 | break; |
153 | break; |
152 | case TLB_INVL_ASID: |
154 | case TLB_INVL_ASID: |
153 | tlb_invalidate_asid(asid); |
155 | tlb_invalidate_asid(asid); |
154 | break; |
156 | break; |
155 | case TLB_INVL_PAGES: |
157 | case TLB_INVL_PAGES: |
156 | ASSERT(count); |
158 | ASSERT(count); |
157 | tlb_invalidate_pages(asid, page, count); |
159 | tlb_invalidate_pages(asid, page, count); |
158 | break; |
160 | break; |
159 | default: |
161 | default: |
160 | panic("unknown type (%d)\n", type); |
162 | panic("unknown type (%d)\n", type); |
161 | break; |
163 | break; |
162 | } |
164 | } |
163 | if (type == TLB_INVL_ALL) |
165 | if (type == TLB_INVL_ALL) |
164 | break; |
166 | break; |
165 | } |
167 | } |
166 | 168 | ||
167 | spinlock_unlock(&CPU->lock); |
169 | spinlock_unlock(&CPU->lock); |
168 | CPU->tlb_active = 1; |
170 | CPU->tlb_active = 1; |
169 | } |
171 | } |
170 | 172 | ||
171 | #endif /* CONFIG_SMP */ |
173 | #endif /* CONFIG_SMP */ |
172 | 174 |