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1
/*
1
/*
2
 * Copyright (c) 2006 Martin Decky
2
 * Copyright (c) 2006 Martin Decky
3
 * Copyright (c) 2009 Jiri Svoboda
3
 * Copyright (c) 2009 Jiri Svoboda
4
 * All rights reserved.
4
 * All rights reserved.
5
 *
5
 *
6
 * Redistribution and use in source and binary forms, with or without
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions
7
 * modification, are permitted provided that the following conditions
8
 * are met:
8
 * are met:
9
 *
9
 *
10
 * - Redistributions of source code must retain the above copyright
10
 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
11
 *   notice, this list of conditions and the following disclaimer.
12
 * - Redistributions in binary form must reproduce the above copyright
12
 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
13
 *   notice, this list of conditions and the following disclaimer in the
14
 *   documentation and/or other materials provided with the distribution.
14
 *   documentation and/or other materials provided with the distribution.
15
 * - The name of the author may not be used to endorse or promote products
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
16
 *   derived from this software without specific prior written permission.
17
 *
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
 */
28
 */
29
 
29
 
30
/** @addtogroup genarch
30
/** @addtogroup genarch
31
 * @{
31
 * @{
32
 */
32
 */
33
/** @file
33
/** @file
34
 */
34
 */
35
 
35
 
36
#include <genarch/drivers/via-cuda/cuda.h>
36
#include <genarch/drivers/via-cuda/cuda.h>
37
#include <console/chardev.h>
37
#include <console/chardev.h>
38
#include <ddi/irq.h>
38
#include <ddi/irq.h>
39
#include <arch/asm.h>
39
#include <arch/asm.h>
40
#include <mm/slab.h>
40
#include <mm/slab.h>
41
#include <ddi/device.h>
41
#include <ddi/device.h>
42
#include <synch/spinlock.h>
42
#include <synch/spinlock.h>
43
 
43
 
-
 
44
static irq_ownership_t cuda_claim(irq_t *irq);
44
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
45
static void cuda_irq_handler(irq_t *irq);
-
 
46
 
45
static void cuda_irq_listen(irq_t *irq);
47
static void cuda_irq_listen(irq_t *irq);
46
static void cuda_irq_receive(irq_t *irq);
48
static void cuda_irq_receive(irq_t *irq);
47
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
49
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
-
 
50
static void cuda_irq_send_start(irq_t *irq);
-
 
51
static void cuda_irq_send(irq_t *irq);
-
 
52
 
-
 
53
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
-
 
54
static void cuda_send_start(cuda_instance_t *instance);
-
 
55
static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
48
 
56
 
49
/** B register fields */
57
/** B register fields */
50
enum {
58
enum {
51
    TREQ    = 0x08,
59
    TREQ    = 0x08,
52
    TACK    = 0x10,
60
    TACK    = 0x10,
53
    TIP = 0x20
61
    TIP = 0x20
54
};
62
};
55
 
63
 
56
/** IER register fields */
64
/** IER register fields */
57
enum {
65
enum {
58
    IER_CLR = 0x00,
66
    IER_CLR = 0x00,
59
    IER_SET = 0x80,
67
    IER_SET = 0x80,
60
 
68
 
61
    SR_INT  = 0x04,
69
    SR_INT  = 0x04,
62
    ALL_INT = 0x7f
70
    ALL_INT = 0x7f
63
};
71
};
64
 
72
 
65
/** ACR register fields */
73
/** ACR register fields */
66
enum {
74
enum {
67
    SR_OUT  = 0x10
75
    SR_OUT  = 0x10
68
};
76
};
69
 
77
 
-
 
78
/** Packet types */
-
 
79
enum {
-
 
80
    PT_ADB  = 0x00,
-
 
81
    PT_CUDA = 0x01
-
 
82
};
-
 
83
 
-
 
84
/** CUDA packet types */
-
 
85
enum {
-
 
86
    CPT_AUTOPOLL    = 0x01
-
 
87
};
-
 
88
 
-
 
89
cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
-
 
90
{
-
 
91
    cuda_instance_t *instance
-
 
92
        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
-
 
93
    if (instance) {
-
 
94
        instance->cuda = dev;
-
 
95
        instance->kbrdin = NULL;
-
 
96
        instance->xstate = cx_listen;
-
 
97
        instance->bidx = 0;
-
 
98
        instance->snd_bytes = 0;
-
 
99
 
-
 
100
        spinlock_initialize(&instance->dev_lock, "cuda_dev");
-
 
101
 
-
 
102
        /* Disable all interrupts from CUDA. */
-
 
103
        pio_write_8(&dev->ier, IER_CLR | ALL_INT);
-
 
104
 
-
 
105
        irq_initialize(&instance->irq);
-
 
106
        instance->irq.devno = device_assign_devno();
-
 
107
        instance->irq.inr = inr;
-
 
108
        instance->irq.claim = cuda_claim;
-
 
109
        instance->irq.handler = cuda_irq_handler;
-
 
110
        instance->irq.instance = instance;
-
 
111
        instance->irq.cir = cir;
-
 
112
        instance->irq.cir_arg = cir_arg;
-
 
113
        instance->irq.preack = true;
-
 
114
    }
-
 
115
   
-
 
116
    return instance;
-
 
117
}
-
 
118
 
70
#include <print.h>
119
#include <print.h>
-
 
120
void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
-
 
121
{
-
 
122
    cuda_t *dev = instance->cuda;
-
 
123
 
-
 
124
    ASSERT(instance);
-
 
125
    ASSERT(kbrdin);
-
 
126
 
-
 
127
    instance->kbrdin = kbrdin;
-
 
128
    irq_register(&instance->irq);
-
 
129
 
-
 
130
    /* Enable SR interrupt. */
-
 
131
    pio_write_8(&dev->ier, TIP | TREQ);
-
 
132
    pio_write_8(&dev->ier, IER_SET | SR_INT);
-
 
133
 
-
 
134
    /* Enable ADB autopolling. */
-
 
135
    cuda_autopoll_set(instance, true);
-
 
136
}
-
 
137
 
71
static irq_ownership_t cuda_claim(irq_t *irq)
138
static irq_ownership_t cuda_claim(irq_t *irq)
72
{
139
{
73
    cuda_instance_t *instance = irq->instance;
140
    cuda_instance_t *instance = irq->instance;
74
    cuda_t *dev = instance->cuda;
141
    cuda_t *dev = instance->cuda;
75
    uint8_t ifr;
142
    uint8_t ifr;
76
 
143
 
-
 
144
    spinlock_lock(&instance->dev_lock);
77
    ifr = pio_read_8(&dev->ifr);
145
    ifr = pio_read_8(&dev->ifr);
-
 
146
    spinlock_unlock(&instance->dev_lock);
78
 
147
 
79
    if ((ifr & SR_INT) == 0)
148
    if ((ifr & SR_INT) == 0)
80
        return IRQ_DECLINE;
149
        return IRQ_DECLINE;
81
 
150
 
82
    return IRQ_ACCEPT;
151
    return IRQ_ACCEPT;
83
}
152
}
84
 
153
 
85
static void cuda_irq_handler(irq_t *irq)
154
static void cuda_irq_handler(irq_t *irq)
86
{
155
{
87
    cuda_instance_t *instance = irq->instance;
156
    cuda_instance_t *instance = irq->instance;
88
    uint8_t rbuf[CUDA_RCV_BUF_SIZE];
157
    uint8_t rbuf[CUDA_RCV_BUF_SIZE];
89
    size_t len;
158
    size_t len;
90
    bool handle;
159
    bool handle;
91
 
160
 
92
    handle = false;
161
    handle = false;
93
    len = 0;
162
    len = 0;
94
 
163
 
95
    spinlock_lock(&instance->dev_lock);
164
    spinlock_lock(&instance->dev_lock);
96
 
165
 
97
    /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
166
    /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
98
    pio_write_8(&instance->cuda->ifr, SR_INT);
167
    pio_write_8(&instance->cuda->ifr, SR_INT);
99
 
168
 
100
    switch (instance->xstate) {
169
    switch (instance->xstate) {
101
    case cx_listen: cuda_irq_listen(irq); break;
170
    case cx_listen: cuda_irq_listen(irq); break;
102
    case cx_receive: cuda_irq_receive(irq); break;
171
    case cx_receive: cuda_irq_receive(irq); break;
103
    case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
172
    case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
104
        handle = true; break;
173
        handle = true; break;
-
 
174
    case cx_send_start: cuda_irq_send_start(irq); break;
-
 
175
    case cx_send: cuda_irq_send(irq); break;
105
    }
176
    }
106
 
177
 
107
    spinlock_unlock(&instance->dev_lock);
178
    spinlock_unlock(&instance->dev_lock);
108
 
179
 
109
    /* Handle an incoming packet. */
180
    /* Handle an incoming packet. */
110
    if (handle)
181
    if (handle)
111
        cuda_packet_handle(instance, rbuf, len);
182
        cuda_packet_handle(instance, rbuf, len);
112
}
183
}
113
 
184
 
114
/** Interrupt in listen state.
185
/** Interrupt in listen state.
115
 *
186
 *
116
 * Start packet reception.
187
 * Start packet reception.
117
 */
188
 */
118
static void cuda_irq_listen(irq_t *irq)
189
static void cuda_irq_listen(irq_t *irq)
119
{
190
{
120
    cuda_instance_t *instance = irq->instance;
191
    cuda_instance_t *instance = irq->instance;
121
    cuda_t *dev = instance->cuda;
192
    cuda_t *dev = instance->cuda;
122
    uint8_t b;
193
    uint8_t b;
123
 
194
 
124
    b = pio_read_8(&dev->b);
195
    b = pio_read_8(&dev->b);
125
 
196
 
126
    if ((b & TREQ) != 0) {
197
    if ((b & TREQ) != 0) {
127
        printf("cuda_irq_listen: no TREQ?!\n");
198
        printf("cuda_irq_listen: no TREQ?!\n");
128
        return;
199
        return;
129
    }
200
    }
130
 
201
 
131
    pio_read_8(&dev->sr);
202
    pio_read_8(&dev->sr);
132
    pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
203
    pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
133
    instance->xstate = cx_receive;
204
    instance->xstate = cx_receive;
134
}
205
}
135
 
206
 
136
/** Interrupt in receive state.
207
/** Interrupt in receive state.
137
 *
208
 *
138
 * Receive next byte of packet.
209
 * Receive next byte of packet.
139
 */
210
 */
140
static void cuda_irq_receive(irq_t *irq)
211
static void cuda_irq_receive(irq_t *irq)
141
{
212
{
142
    cuda_instance_t *instance = irq->instance;
213
    cuda_instance_t *instance = irq->instance;
143
    cuda_t *dev = instance->cuda;
214
    cuda_t *dev = instance->cuda;
144
    uint8_t b, data;
215
    uint8_t b, data;
145
 
216
 
146
    data = pio_read_8(&dev->sr);
217
    data = pio_read_8(&dev->sr);
147
    if (instance->bidx < CUDA_RCV_BUF_SIZE)
218
    if (instance->bidx < CUDA_RCV_BUF_SIZE)
148
        instance->rcv_buf[instance->bidx++] = data;
219
        instance->rcv_buf[instance->bidx++] = data;
149
 
220
 
150
    b = pio_read_8(&dev->b);
221
    b = pio_read_8(&dev->b);
151
 
222
 
152
    if ((b & TREQ) == 0) {
223
    if ((b & TREQ) == 0) {
153
        pio_write_8(&dev->b, b ^ TACK);
224
        pio_write_8(&dev->b, b ^ TACK);
154
    } else {
225
    } else {
155
        pio_write_8(&dev->b, b | TACK | TIP);
226
        pio_write_8(&dev->b, b | TACK | TIP);
156
        instance->xstate = cx_rcv_end;
227
        instance->xstate = cx_rcv_end;
157
    }
228
    }
158
}
229
}
159
 
230
 
160
/** Interrupt in rcv_end state.
231
/** Interrupt in rcv_end state.
161
 *
232
 *
162
 * Terminate packet reception. Either go back to listen state or start
233
 * Terminate packet reception. Either go back to listen state or start
163
 * receiving another packet if CUDA has one for us.
234
 * receiving another packet if CUDA has one for us.
164
 */
235
 */
165
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
236
static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
166
{
237
{
167
    cuda_instance_t *instance = irq->instance;
238
    cuda_instance_t *instance = irq->instance;
168
    cuda_t *dev = instance->cuda;
239
    cuda_t *dev = instance->cuda;
169
    uint8_t data, b;
240
    uint8_t data, b;
170
 
241
 
171
    b = pio_read_8(&dev->b);
242
    b = pio_read_8(&dev->b);
172
    data = pio_read_8(&dev->sr);
243
    data = pio_read_8(&dev->sr);
173
 
244
 
174
    instance->xstate = cx_listen;
-
 
175
 
-
 
176
    if ((b & TREQ) == 0) {
245
    if ((b & TREQ) == 0) {
177
        instance->xstate = cx_receive;
246
        instance->xstate = cx_receive;
178
        pio_write_8(&dev->b, b & ~TIP);
247
        pio_write_8(&dev->b, b & ~TIP);
179
    } else {
248
    } else {
180
        instance->xstate = cx_listen;
249
        instance->xstate = cx_listen;
-
 
250
        cuda_send_start(instance);
181
    }
251
    }
182
 
252
 
183
        memcpy(buf, instance->rcv_buf, instance->bidx);
253
        memcpy(buf, instance->rcv_buf, instance->bidx);
184
        *len = instance->bidx;
254
        *len = instance->bidx;
185
    instance->bidx = 0;
255
    instance->bidx = 0;
186
}
256
}
187
 
257
 
-
 
258
/** Interrupt in send_start state.
-
 
259
 *
-
 
260
 * Process result of sending first byte (and send second on success).
-
 
261
 */
-
 
262
static void cuda_irq_send_start(irq_t *irq)
-
 
263
{
-
 
264
    cuda_instance_t *instance = irq->instance;
-
 
265
    cuda_t *dev = instance->cuda;
-
 
266
    uint8_t b;
-
 
267
 
-
 
268
    b = pio_read_8(&dev->b);
-
 
269
 
-
 
270
    if ((b & TREQ) == 0) {
-
 
271
        /* Collision */
-
 
272
        pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
-
 
273
        pio_read_8(&dev->sr);
-
 
274
        pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
-
 
275
        instance->xstate = cx_listen;
-
 
276
        return;
-
 
277
    }
-
 
278
 
-
 
279
    pio_write_8(&dev->sr, instance->snd_buf[1]);
-
 
280
    pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
-
 
281
    instance->bidx = 2;
-
 
282
 
-
 
283
    instance->xstate = cx_send;
-
 
284
}
-
 
285
 
-
 
286
/** Interrupt in send state.
-
 
287
 *
-
 
288
 * Send next byte or terminate transmission.
-
 
289
 */
-
 
290
static void cuda_irq_send(irq_t *irq)
-
 
291
{
-
 
292
    cuda_instance_t *instance = irq->instance;
-
 
293
    cuda_t *dev = instance->cuda;
-
 
294
 
-
 
295
    if (instance->bidx < instance->snd_bytes) {
-
 
296
        /* Send next byte. */
-
 
297
        pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
-
 
298
        pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
-
 
299
        return;
-
 
300
    }
-
 
301
 
-
 
302
    /* End transfer. */
-
 
303
    instance->snd_bytes = 0;
-
 
304
    instance->bidx = 0;
-
 
305
 
-
 
306
    pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
-
 
307
    pio_read_8(&dev->sr);
-
 
308
    pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
-
 
309
 
-
 
310
    instance->xstate = cx_listen;
-
 
311
    /* TODO: Match reply with request. */
-
 
312
}
-
 
313
 
188
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
314
static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
189
{
315
{
190
    if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
316
    if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
191
        && data[2] != 0x8c))
317
        && data[2] != 0x8c))
192
        return;
318
        return;
193
 
319
 
194
    /* The packet contains one or two scancodes. */
320
    /* The packet contains one or two scancodes. */
195
    if (data[3] != 0xff)
321
    if (data[3] != 0xff)
196
        indev_push_character(instance->kbrdin, data[3]);       
322
        indev_push_character(instance->kbrdin, data[3]);       
197
    if (data[4] != 0xff)
323
    if (data[4] != 0xff)
198
        indev_push_character(instance->kbrdin, data[4]);
324
        indev_push_character(instance->kbrdin, data[4]);
199
}
325
}
200
 
326
 
201
cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
327
static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
202
{
328
{
203
    cuda_instance_t *instance
329
    instance->snd_buf[0] = PT_CUDA;
204
        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
-
 
205
    if (instance) {
-
 
206
        instance->cuda = dev;
330
    instance->snd_buf[1] = CPT_AUTOPOLL;
207
        instance->kbrdin = NULL;
331
    instance->snd_buf[2] = enable ? 0x01 : 0x00;
208
        instance->xstate = cx_listen;
332
    instance->snd_bytes = 3;
209
        instance->bidx = 0;
333
    instance->bidx = 0;
210
 
-
 
211
        spinlock_initialize(&instance->dev_lock, "cuda_dev");
-
 
212
 
-
 
213
        /* Disable all interrupts from CUDA. */
-
 
214
        pio_write_8(&dev->ier, IER_CLR | ALL_INT);
-
 
215
 
334
 
216
        irq_initialize(&instance->irq);
-
 
217
        instance->irq.devno = device_assign_devno();
-
 
218
        instance->irq.inr = inr;
-
 
219
        instance->irq.claim = cuda_claim;
-
 
220
        instance->irq.handler = cuda_irq_handler;
-
 
221
        instance->irq.instance = instance;
-
 
222
        instance->irq.cir = cir;
-
 
223
        instance->irq.cir_arg = cir_arg;
-
 
224
        instance->irq.preack = true;
-
 
225
    }
-
 
226
   
-
 
227
    return instance;
335
    cuda_send_start(instance);
228
}
336
}
229
 
337
 
230
void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
338
static void cuda_send_start(cuda_instance_t *instance)
231
{
339
{
232
    cuda_t *dev = instance->cuda;
340
    cuda_t *dev = instance->cuda;
233
 
341
 
234
    ASSERT(instance);
342
    ASSERT(instance->xstate == cx_listen);
235
    ASSERT(kbrdin);
-
 
236
 
343
 
237
    instance->kbrdin = kbrdin;
344
    if (instance->snd_bytes == 0)
238
    irq_register(&instance->irq);
345
        return;
239
 
346
 
240
    /* Enable SR interrupt. */
347
    /* Check for incoming data. */
241
    pio_write_8(&dev->ier, TIP | TREQ);
348
    if ((pio_read_8(&dev->b) & TREQ) == 0)
-
 
349
        return;
-
 
350
 
-
 
351
    pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
242
    pio_write_8(&dev->ier, IER_SET | SR_INT);
352
    pio_write_8(&dev->sr, instance->snd_buf[0]);
-
 
353
    pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
-
 
354
 
-
 
355
    instance->xstate = cx_send_start;
243
}
356
}
244
 
357
 
-
 
358
 
245
/** @}
359
/** @}
246
 */
360
 */
247
 
361