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1 | /* |
1 | /* |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
2 | * Copyright (c) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup genarch |
29 | /** @addtogroup genarch |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** |
32 | /** |
33 | * @file |
33 | * @file |
34 | * @brief Headers for NS 16550 serial port / keyboard driver. |
34 | * @brief Headers for NS 16550 serial port / keyboard driver. |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #ifndef KERN_NS16550_H_ |
37 | #ifndef KERN_NS16550_H_ |
38 | #define KERN_NS16550_H_ |
38 | #define KERN_NS16550_H_ |
39 | 39 | ||
40 | #include <console/chardev.h> |
40 | #include <console/chardev.h> |
41 | #include <ddi/irq.h> |
41 | #include <ddi/irq.h> |
42 | #include <ipc/irq.h> |
42 | #include <ipc/irq.h> |
43 | 43 | ||
44 | extern void ns16550_init(devno_t, uintptr_t, inr_t, cir_t, void *); |
44 | extern void ns16550_init(devno_t, uintptr_t, inr_t, cir_t, void *); |
45 | extern void ns16550_poll(void); |
45 | extern void ns16550_poll(void); |
46 | extern void ns16550_grab(void); |
46 | extern void ns16550_grab(void); |
47 | extern void ns16550_release(void); |
47 | extern void ns16550_release(void); |
48 | extern char ns16550_key_read(chardev_t *); |
48 | extern char ns16550_key_read(chardev_t *); |
49 | extern irq_ownership_t ns16550_claim(void *); |
49 | extern irq_ownership_t ns16550_claim(void *); |
50 | extern void ns16550_irq_handler(irq_t *); |
50 | extern void ns16550_irq_handler(irq_t *); |
51 | 51 | ||
52 | #include <arch/types.h> |
52 | #include <arch/types.h> |
53 | #ifndef ia64 |
- | |
54 | #include <arch/drivers/kbd.h> |
53 | #include <arch/drivers/kbd.h> |
55 | #endif |
54 | |
56 | /* NS16550 registers */ |
55 | /* NS16550 registers */ |
57 | #define RBR_REG 0 /** Receiver Buffer Register. */ |
56 | #define RBR_REG 0 /** Receiver Buffer Register. */ |
58 | #define IER_REG 1 /** Interrupt Enable Register. */ |
57 | #define IER_REG 1 /** Interrupt Enable Register. */ |
59 | #define IIR_REG 2 /** Interrupt Ident Register (read). */ |
58 | #define IIR_REG 2 /** Interrupt Ident Register (read). */ |
60 | #define FCR_REG 2 /** FIFO control register (write). */ |
59 | #define FCR_REG 2 /** FIFO control register (write). */ |
61 | #define LCR_REG 3 /** Line Control register. */ |
60 | #define LCR_REG 3 /** Line Control register. */ |
62 | #define MCR_REG 4 /** Modem Control Register. */ |
61 | #define MCR_REG 4 /** Modem Control Register. */ |
63 | #define LSR_REG 5 /** Line Status Register. */ |
62 | #define LSR_REG 5 /** Line Status Register. */ |
64 | 63 | ||
65 | #define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */ |
64 | #define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */ |
66 | 65 | ||
67 | #define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
66 | #define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
68 | 67 | ||
69 | #define MCR_OUT2 0x08 /** OUT2. */ |
68 | #define MCR_OUT2 0x08 /** OUT2. */ |
70 | 69 | ||
71 | /** Structure representing the ns16550 device. */ |
70 | /** Structure representing the ns16550 device. */ |
72 | typedef struct { |
71 | typedef struct { |
73 | devno_t devno; |
72 | devno_t devno; |
74 | /** Memory mapped registers of the ns16550. */ |
73 | /** Memory mapped registers of the ns16550. */ |
75 | volatile ioport_t io_port; |
74 | volatile ioport_t io_port; |
76 | } ns16550_t; |
75 | } ns16550_t; |
77 | 76 | ||
78 | static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
77 | static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
79 | { |
78 | { |
80 | return pio_read_8(dev->io_port + RBR_REG); |
79 | return pio_read_8(dev->io_port + RBR_REG); |
81 | } |
80 | } |
82 | static inline void ns16550_rbr_write(ns16550_t *dev, uint8_t v) |
81 | static inline void ns16550_rbr_write(ns16550_t *dev, uint8_t v) |
83 | { |
82 | { |
84 | pio_write_8(dev->io_port + RBR_REG, v); |
83 | pio_write_8(dev->io_port + RBR_REG, v); |
85 | } |
84 | } |
86 | 85 | ||
87 | static inline uint8_t ns16550_ier_read(ns16550_t *dev) |
86 | static inline uint8_t ns16550_ier_read(ns16550_t *dev) |
88 | { |
87 | { |
89 | return pio_read_8(dev->io_port + IER_REG); |
88 | return pio_read_8(dev->io_port + IER_REG); |
90 | } |
89 | } |
91 | 90 | ||
92 | static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) |
91 | static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) |
93 | { |
92 | { |
94 | pio_write_8(dev->io_port + IER_REG, v); |
93 | pio_write_8(dev->io_port + IER_REG, v); |
95 | } |
94 | } |
96 | 95 | ||
97 | static inline uint8_t ns16550_iir_read(ns16550_t *dev) |
96 | static inline uint8_t ns16550_iir_read(ns16550_t *dev) |
98 | { |
97 | { |
99 | return pio_read_8(dev->io_port + IIR_REG); |
98 | return pio_read_8(dev->io_port + IIR_REG); |
100 | } |
99 | } |
101 | 100 | ||
102 | static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) |
101 | static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) |
103 | { |
102 | { |
104 | pio_write_8(dev->io_port + FCR_REG, v); |
103 | pio_write_8(dev->io_port + FCR_REG, v); |
105 | } |
104 | } |
106 | 105 | ||
107 | static inline uint8_t ns16550_lcr_read(ns16550_t *dev) |
106 | static inline uint8_t ns16550_lcr_read(ns16550_t *dev) |
108 | { |
107 | { |
109 | return pio_read_8(dev->io_port + LCR_REG); |
108 | return pio_read_8(dev->io_port + LCR_REG); |
110 | } |
109 | } |
111 | 110 | ||
112 | static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) |
111 | static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) |
113 | { |
112 | { |
114 | pio_write_8(dev->io_port + LCR_REG, v); |
113 | pio_write_8(dev->io_port + LCR_REG, v); |
115 | } |
114 | } |
116 | 115 | ||
117 | static inline uint8_t ns16550_lsr_read(ns16550_t *dev) |
116 | static inline uint8_t ns16550_lsr_read(ns16550_t *dev) |
118 | { |
117 | { |
119 | return pio_read_8(dev->io_port + LSR_REG); |
118 | return pio_read_8(dev->io_port + LSR_REG); |
120 | } |
119 | } |
121 | 120 | ||
122 | static inline uint8_t ns16550_mcr_read(ns16550_t *dev) |
121 | static inline uint8_t ns16550_mcr_read(ns16550_t *dev) |
123 | { |
122 | { |
124 | return pio_read_8(dev->io_port + MCR_REG); |
123 | return pio_read_8(dev->io_port + MCR_REG); |
125 | } |
124 | } |
126 | 125 | ||
127 | static inline void ns16550_mcr_write(ns16550_t *dev, uint8_t v) |
126 | static inline void ns16550_mcr_write(ns16550_t *dev, uint8_t v) |
128 | { |
127 | { |
129 | pio_write_8(dev->io_port + MCR_REG, v); |
128 | pio_write_8(dev->io_port + MCR_REG, v); |
130 | } |
129 | } |
131 | 130 | ||
132 | #endif |
131 | #endif |
133 | 132 | ||
134 | /** @} |
133 | /** @} |
135 | */ |
134 | */ |
136 | 135 |