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| 1 | /* |
1 | /* |
| 2 | * Copyright (C) 2006 Martin Decky |
2 | * Copyright (C) 2006 Martin Decky |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __xen32_HYPERCALL_H__ |
29 | #ifndef __xen32_HYPERCALL_H__ |
| 30 | #define __xen32_HYPERCALL_H__ |
30 | #define __xen32_HYPERCALL_H__ |
| 31 | 31 | ||
| 32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
| 33 | #include <macros.h> |
33 | #include <macros.h> |
| 34 | 34 | ||
| 35 | 35 | ||
| - | 36 | typedef uint16_t domid_t; |
|
| - | 37 | ||
| - | 38 | typedef struct { |
|
| - | 39 | uint64_t ptr; /**< Machine address of PTE */ |
|
| - | 40 | uint64_t val; /**< New contents of PTE */ |
|
| - | 41 | } mmu_update_t; |
|
| - | 42 | ||
| - | 43 | typedef struct { |
|
| - | 44 | unsigned int cmd; |
|
| - | 45 | union { |
|
| - | 46 | unsigned long mfn; |
|
| - | 47 | unsigned long linear_addr; |
|
| - | 48 | } arg1; |
|
| - | 49 | union { |
|
| - | 50 | unsigned int nr_ents; |
|
| - | 51 | void *vcpumask; |
|
| - | 52 | } arg2; |
|
| - | 53 | } mmuext_op_t; |
|
| - | 54 | ||
| - | 55 | ||
| - | 56 | #define XEN_MMU_UPDATE 1 |
|
| 36 | #define XEN_CONSOLE_IO 18 |
57 | #define XEN_CONSOLE_IO 18 |
| - | 58 | #define XEN_MMUEXT_OP 26 |
|
| 37 | 59 | ||
| 38 | 60 | ||
| 39 | /* |
61 | /* |
| 40 | * Commands for XEN_CONSOLE_IO |
62 | * Commands for XEN_CONSOLE_IO |
| 41 | */ |
63 | */ |
| 42 | #define CONSOLE_IO_WRITE 0 |
64 | #define CONSOLE_IO_WRITE 0 |
| 43 | #define CONSOLE_IO_READ 1 |
65 | #define CONSOLE_IO_READ 1 |
| 44 | 66 | ||
| 45 | 67 | ||
| - | 68 | #define MMUEXT_PIN_L1_TABLE 0 |
|
| - | 69 | #define MMUEXT_PIN_L2_TABLE 1 |
|
| - | 70 | #define MMUEXT_PIN_L3_TABLE 2 |
|
| - | 71 | #define MMUEXT_PIN_L4_TABLE 3 |
|
| - | 72 | #define MMUEXT_UNPIN_TABLE 4 |
|
| - | 73 | #define MMUEXT_NEW_BASEPTR 5 |
|
| - | 74 | #define MMUEXT_TLB_FLUSH_LOCAL 6 |
|
| - | 75 | #define MMUEXT_INVLPG_LOCAL 7 |
|
| - | 76 | #define MMUEXT_TLB_FLUSH_MULTI 8 |
|
| - | 77 | #define MMUEXT_INVLPG_MULTI 9 |
|
| - | 78 | #define MMUEXT_TLB_FLUSH_ALL 10 |
|
| - | 79 | #define MMUEXT_INVLPG_ALL 11 |
|
| - | 80 | #define MMUEXT_FLUSH_CACHE 12 |
|
| - | 81 | #define MMUEXT_SET_LDT 13 |
|
| - | 82 | #define MMUEXT_NEW_USER_BASEPTR 15 |
|
| - | 83 | ||
| - | 84 | ||
| - | 85 | #define DOMID_SELF (0x7FF0U) |
|
| - | 86 | #define DOMID_IO (0x7FF1U) |
|
| - | 87 | ||
| - | 88 | ||
| 46 | #define hypercall0(id) \ |
89 | #define hypercall0(id) \ |
| 47 | ({ \ |
90 | ({ \ |
| 48 | unative_t ret; \ |
91 | unative_t ret; \ |
| 49 | asm volatile ( \ |
92 | asm volatile ( \ |
| 50 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
93 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 51 | : "=a" (ret) \ |
94 | : "=a" (ret) \ |
| 52 | : \ |
95 | : \ |
| 53 | : "memory" \ |
96 | : "memory" \ |
| 54 | ); \ |
97 | ); \ |
| 55 | ret; \ |
98 | ret; \ |
| 56 | }) |
99 | }) |
| 57 | 100 | ||
| 58 | #define hypercall1(id, p1) \ |
101 | #define hypercall1(id, p1) \ |
| 59 | ({ \ |
102 | ({ \ |
| 60 | unative_t ret, __ign1; \ |
103 | unative_t ret, __ign1; \ |
| 61 | asm volatile ( \ |
104 | asm volatile ( \ |
| 62 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
105 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 63 | : "=a" (ret), \ |
106 | : "=a" (ret), \ |
| 64 | "=b" (__ign1) \ |
107 | "=b" (__ign1) \ |
| 65 | : "1" (p1) \ |
108 | : "1" (p1) \ |
| 66 | : "memory" \ |
109 | : "memory" \ |
| 67 | ); \ |
110 | ); \ |
| 68 | ret; \ |
111 | ret; \ |
| 69 | }) |
112 | }) |
| 70 | 113 | ||
| 71 | #define hypercall2(id, p1, p2) \ |
114 | #define hypercall2(id, p1, p2) \ |
| 72 | ({ \ |
115 | ({ \ |
| 73 | unative_t ret, __ign1, __ign2; \ |
116 | unative_t ret, __ign1, __ign2; \ |
| 74 | asm volatile ( \ |
117 | asm volatile ( \ |
| 75 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
118 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 76 | : "=a" (ret), \ |
119 | : "=a" (ret), \ |
| 77 | "=b" (__ign1), \ |
120 | "=b" (__ign1), \ |
| 78 | "=c" (__ign2) \ |
121 | "=c" (__ign2) \ |
| 79 | : "1" (p1), \ |
122 | : "1" (p1), \ |
| 80 | "2" (p2) \ |
123 | "2" (p2) \ |
| 81 | : "memory" \ |
124 | : "memory" \ |
| 82 | ); \ |
125 | ); \ |
| 83 | ret; \ |
126 | ret; \ |
| 84 | }) |
127 | }) |
| 85 | 128 | ||
| 86 | #define hypercall3(id, p1, p2, p3) \ |
129 | #define hypercall3(id, p1, p2, p3) \ |
| 87 | ({ \ |
130 | ({ \ |
| 88 | unative_t ret, __ign1, __ign2, __ign3; \ |
131 | unative_t ret, __ign1, __ign2, __ign3; \ |
| 89 | asm volatile ( \ |
132 | asm volatile ( \ |
| 90 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
133 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 91 | : "=a" (ret), \ |
134 | : "=a" (ret), \ |
| 92 | "=b" (__ign1), \ |
135 | "=b" (__ign1), \ |
| 93 | "=c" (__ign2), \ |
136 | "=c" (__ign2), \ |
| 94 | "=d" (__ign3) \ |
137 | "=d" (__ign3) \ |
| 95 | : "1" (p1), \ |
138 | : "1" (p1), \ |
| 96 | "2" (p2), \ |
139 | "2" (p2), \ |
| 97 | "3" (p3) \ |
140 | "3" (p3) \ |
| 98 | : "memory" \ |
141 | : "memory" \ |
| 99 | ); \ |
142 | ); \ |
| 100 | ret; \ |
143 | ret; \ |
| 101 | }) |
144 | }) |
| 102 | 145 | ||
| 103 | #define hypercall4(id, p1, p2, p3, p4) \ |
146 | #define hypercall4(id, p1, p2, p3, p4) \ |
| 104 | ({ \ |
147 | ({ \ |
| 105 | unative_t ret, __ign1, __ign2, __ign3, __ign4; \ |
148 | unative_t ret, __ign1, __ign2, __ign3, __ign4; \ |
| 106 | asm volatile ( \ |
149 | asm volatile ( \ |
| 107 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
150 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 108 | : "=a" (ret), \ |
151 | : "=a" (ret), \ |
| 109 | "=b" (__ign1), \ |
152 | "=b" (__ign1), \ |
| 110 | "=c" (__ign2), \ |
153 | "=c" (__ign2), \ |
| 111 | "=d" (__ign3), \ |
154 | "=d" (__ign3), \ |
| 112 | "=S" (__ign4) \ |
155 | "=S" (__ign4) \ |
| 113 | : "1" (p1), \ |
156 | : "1" (p1), \ |
| 114 | "2" (p2), \ |
157 | "2" (p2), \ |
| 115 | "3" (p3), \ |
158 | "3" (p3), \ |
| 116 | "4" (p4) \ |
159 | "4" (p4) \ |
| 117 | : "memory" \ |
160 | : "memory" \ |
| 118 | ); \ |
161 | ); \ |
| 119 | ret; \ |
162 | ret; \ |
| 120 | }) |
163 | }) |
| 121 | 164 | ||
| 122 | #define hypercall5(id, p1, p2, p3, p4, p5) \ |
165 | #define hypercall5(id, p1, p2, p3, p4, p5) \ |
| 123 | ({ \ |
166 | ({ \ |
| 124 | unative_t ret, __ign1, __ign2, __ign3, __ign4, __ign5; \ |
167 | unative_t ret, __ign1, __ign2, __ign3, __ign4, __ign5; \ |
| 125 | asm volatile ( \ |
168 | asm volatile ( \ |
| 126 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
169 | "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| 127 | : "=a" (ret), \ |
170 | : "=a" (ret), \ |
| 128 | "=b" (__ign1), \ |
171 | "=b" (__ign1), \ |
| 129 | "=c" (__ign2), \ |
172 | "=c" (__ign2), \ |
| 130 | "=d" (__ign3), \ |
173 | "=d" (__ign3), \ |
| 131 | "=S" (__ign4), \ |
174 | "=S" (__ign4), \ |
| 132 | "=D" (__ign5) \ |
175 | "=D" (__ign5) \ |
| 133 | : "1" (p1), \ |
176 | : "1" (p1), \ |
| 134 | "2" (p2), \ |
177 | "2" (p2), \ |
| 135 | "3" (p3), \ |
178 | "3" (p3), \ |
| 136 | "4" (p4), \ |
179 | "4" (p4), \ |
| 137 | "5" (p5) \ |
180 | "5" (p5) \ |
| 138 | : "memory" \ |
181 | : "memory" \ |
| 139 | ); \ |
182 | ); \ |
| 140 | ret; \ |
183 | ret; \ |
| 141 | }) |
184 | }) |
| 142 | 185 | ||
| 143 | 186 | ||
| 144 | static inline int xen_console_io(const int cmd, const int count, const char *str) |
187 | static inline int xen_console_io(const unsigned int cmd, const unsigned int count, const char *str) |
| 145 | { |
188 | { |
| 146 | return hypercall3(XEN_CONSOLE_IO, cmd, count, str); |
189 | return hypercall3(XEN_CONSOLE_IO, cmd, count, str); |
| 147 | } |
190 | } |
| - | 191 | ||
| - | 192 | static inline int xen_mmu_update(const mmu_update_t *req, const unsigned int count, unsigned int *success_count, domid_t domid) |
|
| - | 193 | { |
|
| - | 194 | return hypercall4(XEN_MMU_UPDATE, req, count, success_count, domid); |
|
| - | 195 | } |
|
| - | 196 | ||
| - | 197 | static inline int xen_mmuext_op(const mmuext_op_t *op, const unsigned int count, unsigned int *success_count, domid_t domid) |
|
| - | 198 | { |
|
| - | 199 | return hypercall4(XEN_MMUEXT_OP, op, count, success_count, domid); |
|
| - | 200 | } |
|
| 148 | 201 | ||
| 149 | #endif |
202 | #endif |
| 150 | 203 | ||