WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/trap/trap_table.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
/**
 * This file contains kernel trap table.
 */
 
.register %g2, #scratch
.register %g3, #scratch
.register %g6, #scratch
.register %g7, #scratch 
 
.text
 
#include <arch/trap/trap_table.h>
#include <arch/trap/regwin.h>
#include <arch/trap/interrupt.h>
#include <arch/trap/exception.h>
#include <arch/trap/mmu.h>
#include <arch/stack.h>
#include <arch/regdef.h>
 
#define TABLE_SIZE	TRAP_TABLE_SIZE
#define ENTRY_SIZE	TRAP_TABLE_ENTRY_SIZE
 
/*
 * Kernel trap table.
 */
.align TABLE_SIZE
.global trap_table
trap_table:
 
/* TT = 0x08, TL = 0, instruction_access_exception */
.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
.global instruction_access_exception
instruction_access_exception:
	SIMPLE_HANDLER do_instruction_access_exc
 
/* TT = 0x10, TL = 0, illegal_instruction */
.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
.global illegal_instruction
illegal_instruction:
	SIMPLE_HANDLER do_illegal_instruction
 
/* TT = 0x24, TL = 0, clean_window handler */
.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
.global clean_window_handler
clean_window_handler:
	CLEAN_WINDOW_HANDLER
 
/* TT = 0x32, TL = 0, data_access_error */
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
.global data_access_error
data_access_error:
	SIMPLE_HANDLER do_data_access_error
 
/* TT = 0x34, TL = 0, mem_address_not_aligned */
.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
.global mem_address_not_aligned
mem_address_not_aligned:
	SIMPLE_HANDLER do_mem_address_not_aligned
 
/* TT = 0x41, TL = 0, interrupt_level_1 handler */
.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
.global interrupt_level_1_handler
interrupt_level_1_handler:
	INTERRUPT_LEVEL_N_HANDLER 1
 
/* TT = 0x42, TL = 0, interrupt_level_2 handler */
.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
.global interrupt_level_2_handler
interrupt_level_2_handler:
	INTERRUPT_LEVEL_N_HANDLER 2
 
/* TT = 0x43, TL = 0, interrupt_level_3 handler */
.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
.global interrupt_level_3_handler
interrupt_level_3_handler:
	INTERRUPT_LEVEL_N_HANDLER 3
 
/* TT = 0x44, TL = 0, interrupt_level_4 handler */
.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
.global interrupt_level_4_handler
interrupt_level_4_handler:
	INTERRUPT_LEVEL_N_HANDLER 4
 
/* TT = 0x45, TL = 0, interrupt_level_5 handler */
.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
.global interrupt_level_5_handler
interrupt_level_5_handler:
	INTERRUPT_LEVEL_N_HANDLER 5
 
/* TT = 0x46, TL = 0, interrupt_level_6 handler */
.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
.global interrupt_level_6_handler
interrupt_level_6_handler:
	INTERRUPT_LEVEL_N_HANDLER 6
 
/* TT = 0x47, TL = 0, interrupt_level_7 handler */
.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
.global interrupt_level_7_handler
interrupt_level_7_handler:
	INTERRUPT_LEVEL_N_HANDLER 7
 
/* TT = 0x48, TL = 0, interrupt_level_8 handler */
.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
.global interrupt_level_8_handler
interrupt_level_8_handler:
	INTERRUPT_LEVEL_N_HANDLER 8
 
/* TT = 0x49, TL = 0, interrupt_level_9 handler */
.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
.global interrupt_level_9_handler
interrupt_level_9_handler:
	INTERRUPT_LEVEL_N_HANDLER 9
 
/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
.global interrupt_level_10_handler
interrupt_level_10_handler:
	INTERRUPT_LEVEL_N_HANDLER 10
 
/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
.global interrupt_level_11_handler
interrupt_level_11_handler:
	INTERRUPT_LEVEL_N_HANDLER 11
 
/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
.global interrupt_level_12_handler
interrupt_level_12_handler:
	INTERRUPT_LEVEL_N_HANDLER 12
 
/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
.global interrupt_level_13_handler
interrupt_level_13_handler:
	INTERRUPT_LEVEL_N_HANDLER 13
 
/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
.global interrupt_level_14_handler
interrupt_level_14_handler:
	INTERRUPT_LEVEL_N_HANDLER 14
 
/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
.global interrupt_level_15_handler
interrupt_level_15_handler:
	INTERRUPT_LEVEL_N_HANDLER 15
 
/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
.global interrupt_vector_trap_handler
interrupt_vector_trap_handler:
	INTERRUPT_VECTOR_TRAP_HANDLER
 
/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
.global fast_instruction_access_mmu_miss_handler
fast_instruction_access_mmu_miss_handler:
	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
 
/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
.global fast_data_access_mmu_miss_handler
fast_data_access_mmu_miss_handler:
	FAST_DATA_ACCESS_MMU_MISS_HANDLER
 
/* TT = 0x6c, TL = 0, fast_data_access_protection */
.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
.global fast_data_access_protection_handler
fast_data_access_protection_handler:
	FAST_DATA_ACCESS_PROTECTION_HANDLER
 
/* TT = 0x80, TL = 0, spill_0_normal handler */
.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
.global spill_0_normal
spill_0_normal:
	SPILL_NORMAL_HANDLER
 
/* TT = 0xc0, TL = 0, fill_0_normal handler */
.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
.global fill_0_normal
fill_0_normal:
	FILL_NORMAL_HANDLER
 
/*
 * Handlers for TL>0.
 */
 
/* TT = 0x08, TL > 0, instruction_access_exception */
.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
.global instruction_access_exception_high
instruction_access_exception_high:
	SIMPLE_HANDLER do_instruction_access_exc
 
/* TT = 0x10, TL > 0, illegal_instruction */
.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
.global illegal_instruction_high
illegal_instruction_high:
	SIMPLE_HANDLER do_illegal_instruction
 
/* TT = 0x24, TL > 0, clean_window handler */
.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
.global clean_window_handler_high
clean_window_handler_high:
	CLEAN_WINDOW_HANDLER
 
/* TT = 0x32, TL > 0, data_access_error */
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
.global data_access_error_high
data_access_error_high:
	SIMPLE_HANDLER do_data_access_error
 
/* TT = 0x34, TL > 0, mem_address_not_aligned */
.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
.global mem_address_not_aligned_high
mem_address_not_aligned_high:
	SIMPLE_HANDLER do_mem_address_not_aligned
 
/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
.global fast_instruction_access_mmu_miss_handler_high
fast_instruction_access_mmu_miss_handler_high:
	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
 
/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
.global fast_data_access_mmu_miss_handler_high
fast_data_access_mmu_miss_handler_high:
	FAST_DATA_ACCESS_MMU_MISS_HANDLER
 
/* TT = 0x6c, TL > 0, fast_data_access_protection */
.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
.global fast_data_access_protection_handler_high
fast_data_access_protection_handler_high:
	FAST_DATA_ACCESS_PROTECTION_HANDLER
 
/* TT = 0x80, TL > 0, spill_0_normal handler */
.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
.global spill_0_normal_high
spill_0_normal_high:
	SPILL_NORMAL_HANDLER
 
/* TT = 0xc0, TL > 0, fill_0_normal handler */
.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
.global fill_0_normal_high
fill_0_normal_high:
	FILL_NORMAL_HANDLER
 
 
/* Preemptible trap handler for TL=1.
 *
 * This trap handler makes arrangements to make calling of scheduler() from
 * within a trap context possible. It is guaranteed to function only when traps
 * are not nested (i.e. for TL=1).
 *
 * Every trap handler on TL=1 that makes a call to the scheduler needs to
 * be based on this function. The reason behind it is that the nested
 * trap levels and the automatic saving of the interrupted context by hardware
 * does not work well together with scheduling (i.e. a thread cannot be rescheduled
 * with TL>0). Therefore it is necessary to eliminate the effect of trap levels
 * by software and save the necessary state on the kernel stack.
 *
 * Note that for traps with TL>1, more state needs to be saved. This function
 * is therefore not going to work when TL>1.
 *
 * The caller is responsible for doing SAVE and allocating
 * PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE bytes on the stack.
 
 *
 * Input registers:
 * 	%l0	 	Address of function to call.
 * Output registers:
 *	 %l1 - %l7 	Copy of %g1 - %g7
 */
.global preemptible_handler
preemptible_handler:
	/*
	 * Save TSTATE, TPC, TNPC and PSTATE aside.
	 */
	rdpr %tstate, %g1
	rdpr %tpc, %g2
	rdpr %tnpc, %g3
	rdpr %pstate, %g4
 
	/*
	 * The following memory accesses will not fault
	 * because special provisions are made to have
	 * the kernel stack of THREAD locked in DTLB.
	 */
	stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
	stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
	stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]
	stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]
	
	/*
	 * Write 0 to TL.
	 */
	wrpr %g0, 0, %tl
	
	/*
	 * Alter PSTATE.
	 * - switch to normal globals.
	 */
	and %g4, ~(PSTATE_AG_BIT|PSTATE_IG_BIT|PSTATE_MG_BIT), %g4
	wrpr %g4, 0, %pstate
	 
	/*
	 * Save the normal globals.
	 */
	SAVE_GLOBALS
	
	/*
	 * Call the higher-level handler.
	 */
	mov %fp, %o1				! calculate istate address
	call %l0
 
	add %o1, STACK_BIAS + SAVED_PSTATE, %o1	! calculate istate address
	
	/*
	 * Restore	 the normal global register set.
	 */
	RESTORE_GLOBALS
	
	/*
	 * Restore PSTATE from saved copy.
	 * Alternate/Interrupt/MM globals become active.
	 */
	ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
	wrpr %l4, 0, %pstate
	
	/*
	 * Write 1 to TL.
	 */
	wrpr %g0, 1, %tl
	
	/*
	 * Read TSTATE, TPC and TNPC from saved copy.
	 */
	ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1
	ldx [%fp + STACK_BIAS + SAVED_TPC], %g2
	ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3
 
	/*
	 * Do restore to match the save instruction from the top-level handler.
	 */
	restore
 
	/*
	 * On execution of the RETRY instruction, CWP will be restored from the TSTATE
	 * register. However, because of scheduling, it is possible that CWP in the saved
	 * TSTATE is different from the current CWP. The following chunk of code fixes
	 * CWP in the saved copy of TSTATE.
	 */
	rdpr %cwp, %g4		! read current CWP
	and %g1, ~0x1f, %g1	! clear CWP field in saved TSTATE
	or %g1, %g4, %g1	! write current CWP to TSTATE
	
	/*
	 * Restore TSTATE, TPC and TNPC from saved copies.
	 */
	wrpr %g1, 0, %tstate
	wrpr %g2, 0, %tpc
	wrpr %g3, 0, %tnpc
	 
	/*
	 * Return from interrupt.
	 */
	retry
 

Rev 1787	Rev 1851
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	/**	29	/**
30	* This file contains kernel trap table.	30	* This file contains kernel trap table.
31	*/	31	*/
32		32
33	.register %g2, #scratch	33	.register %g2, #scratch
34	.register %g3, #scratch	34	.register %g3, #scratch
35	.register %g6, #scratch	35	.register %g6, #scratch
36	.register %g7, #scratch	36	.register %g7, #scratch
37		37
38	.text	38	.text
39		39
40	#include <arch/trap/trap_table.h>	40	#include <arch/trap/trap_table.h>
41	#include <arch/trap/regwin.h>	41	#include <arch/trap/regwin.h>
42	#include <arch/trap/interrupt.h>	42	#include <arch/trap/interrupt.h>
43	#include <arch/trap/exception.h>	43	#include <arch/trap/exception.h>
44	#include <arch/trap/mmu.h>	44	#include <arch/trap/mmu.h>
45	#include <arch/stack.h>	45	#include <arch/stack.h>
-		46	#include <arch/regdef.h>
46		47
47	#define TABLE_SIZE TRAP_TABLE_SIZE	48	#define TABLE_SIZE TRAP_TABLE_SIZE
48	#define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE	49	#define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE
49		50
50	/*	51	/*
51	* Kernel trap table.	52	* Kernel trap table.
52	*/	53	*/
53	.align TABLE_SIZE	54	.align TABLE_SIZE
54	.global trap_table	55	.global trap_table
55	trap_table:	56	trap_table:
56		57
57	/* TT = 0x08, TL = 0, instruction_access_exception */	58	/* TT = 0x08, TL = 0, instruction_access_exception */
58	.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE	59	.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
59	.global instruction_access_exception	60	.global instruction_access_exception
60	instruction_access_exception:	61	instruction_access_exception:
61	SIMPLE_HANDLER do_instruction_access_exc	62	SIMPLE_HANDLER do_instruction_access_exc
62		63
63	/* TT = 0x10, TL = 0, illegal_instruction */	64	/* TT = 0x10, TL = 0, illegal_instruction */
64	.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE	65	.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
65	.global illegal_instruction	66	.global illegal_instruction
66	illegal_instruction:	67	illegal_instruction:
67	SIMPLE_HANDLER do_illegal_instruction	68	SIMPLE_HANDLER do_illegal_instruction
68		69
69	/* TT = 0x24, TL = 0, clean_window handler */	70	/* TT = 0x24, TL = 0, clean_window handler */
70	.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE	71	.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
71	.global clean_window_handler	72	.global clean_window_handler
72	clean_window_handler:	73	clean_window_handler:
73	CLEAN_WINDOW_HANDLER	74	CLEAN_WINDOW_HANDLER
74		75
75	/* TT = 0x32, TL = 0, data_access_error */	76	/* TT = 0x32, TL = 0, data_access_error */
76	.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE	77	.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
77	.global data_access_error	78	.global data_access_error
78	data_access_error:	79	data_access_error:
79	SIMPLE_HANDLER do_data_access_error	80	SIMPLE_HANDLER do_data_access_error
80		81
81	/* TT = 0x34, TL = 0, mem_address_not_aligned */	82	/* TT = 0x34, TL = 0, mem_address_not_aligned */
82	.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE	83	.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
83	.global mem_address_not_aligned	84	.global mem_address_not_aligned
84	mem_address_not_aligned:	85	mem_address_not_aligned:
85	SIMPLE_HANDLER do_mem_address_not_aligned	86	SIMPLE_HANDLER do_mem_address_not_aligned
86		87
87	/* TT = 0x41, TL = 0, interrupt_level_1 handler */	88	/* TT = 0x41, TL = 0, interrupt_level_1 handler */
88	.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE	89	.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
89	.global interrupt_level_1_handler	90	.global interrupt_level_1_handler
90	interrupt_level_1_handler:	91	interrupt_level_1_handler:
91	INTERRUPT_LEVEL_N_HANDLER 1	92	INTERRUPT_LEVEL_N_HANDLER 1
92		93
93	/* TT = 0x42, TL = 0, interrupt_level_2 handler */	94	/* TT = 0x42, TL = 0, interrupt_level_2 handler */
94	.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE	95	.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
95	.global interrupt_level_2_handler	96	.global interrupt_level_2_handler
96	interrupt_level_2_handler:	97	interrupt_level_2_handler:
97	INTERRUPT_LEVEL_N_HANDLER 2	98	INTERRUPT_LEVEL_N_HANDLER 2
98		99
99	/* TT = 0x43, TL = 0, interrupt_level_3 handler */	100	/* TT = 0x43, TL = 0, interrupt_level_3 handler */
100	.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE	101	.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
101	.global interrupt_level_3_handler	102	.global interrupt_level_3_handler
102	interrupt_level_3_handler:	103	interrupt_level_3_handler:
103	INTERRUPT_LEVEL_N_HANDLER 3	104	INTERRUPT_LEVEL_N_HANDLER 3
104		105
105	/* TT = 0x44, TL = 0, interrupt_level_4 handler */	106	/* TT = 0x44, TL = 0, interrupt_level_4 handler */
106	.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE	107	.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
107	.global interrupt_level_4_handler	108	.global interrupt_level_4_handler
108	interrupt_level_4_handler:	109	interrupt_level_4_handler:
109	INTERRUPT_LEVEL_N_HANDLER 4	110	INTERRUPT_LEVEL_N_HANDLER 4
110		111
111	/* TT = 0x45, TL = 0, interrupt_level_5 handler */	112	/* TT = 0x45, TL = 0, interrupt_level_5 handler */
112	.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE	113	.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
113	.global interrupt_level_5_handler	114	.global interrupt_level_5_handler
114	interrupt_level_5_handler:	115	interrupt_level_5_handler:
115	INTERRUPT_LEVEL_N_HANDLER 5	116	INTERRUPT_LEVEL_N_HANDLER 5
116		117
117	/* TT = 0x46, TL = 0, interrupt_level_6 handler */	118	/* TT = 0x46, TL = 0, interrupt_level_6 handler */
118	.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE	119	.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
119	.global interrupt_level_6_handler	120	.global interrupt_level_6_handler
120	interrupt_level_6_handler:	121	interrupt_level_6_handler:
121	INTERRUPT_LEVEL_N_HANDLER 6	122	INTERRUPT_LEVEL_N_HANDLER 6
122		123
123	/* TT = 0x47, TL = 0, interrupt_level_7 handler */	124	/* TT = 0x47, TL = 0, interrupt_level_7 handler */
124	.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE	125	.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
125	.global interrupt_level_7_handler	126	.global interrupt_level_7_handler
126	interrupt_level_7_handler:	127	interrupt_level_7_handler:
127	INTERRUPT_LEVEL_N_HANDLER 7	128	INTERRUPT_LEVEL_N_HANDLER 7
128		129
129	/* TT = 0x48, TL = 0, interrupt_level_8 handler */	130	/* TT = 0x48, TL = 0, interrupt_level_8 handler */
130	.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE	131	.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
131	.global interrupt_level_8_handler	132	.global interrupt_level_8_handler
132	interrupt_level_8_handler:	133	interrupt_level_8_handler:
133	INTERRUPT_LEVEL_N_HANDLER 8	134	INTERRUPT_LEVEL_N_HANDLER 8
134		135
135	/* TT = 0x49, TL = 0, interrupt_level_9 handler */	136	/* TT = 0x49, TL = 0, interrupt_level_9 handler */
136	.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE	137	.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
137	.global interrupt_level_9_handler	138	.global interrupt_level_9_handler
138	interrupt_level_9_handler:	139	interrupt_level_9_handler:
139	INTERRUPT_LEVEL_N_HANDLER 9	140	INTERRUPT_LEVEL_N_HANDLER 9
140		141
141	/* TT = 0x4a, TL = 0, interrupt_level_10 handler */	142	/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
142	.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE	143	.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
143	.global interrupt_level_10_handler	144	.global interrupt_level_10_handler
144	interrupt_level_10_handler:	145	interrupt_level_10_handler:
145	INTERRUPT_LEVEL_N_HANDLER 10	146	INTERRUPT_LEVEL_N_HANDLER 10
146		147
147	/* TT = 0x4b, TL = 0, interrupt_level_11 handler */	148	/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
148	.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE	149	.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
149	.global interrupt_level_11_handler	150	.global interrupt_level_11_handler
150	interrupt_level_11_handler:	151	interrupt_level_11_handler:
151	INTERRUPT_LEVEL_N_HANDLER 11	152	INTERRUPT_LEVEL_N_HANDLER 11
152		153
153	/* TT = 0x4c, TL = 0, interrupt_level_12 handler */	154	/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
154	.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE	155	.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
155	.global interrupt_level_12_handler	156	.global interrupt_level_12_handler
156	interrupt_level_12_handler:	157	interrupt_level_12_handler:
157	INTERRUPT_LEVEL_N_HANDLER 12	158	INTERRUPT_LEVEL_N_HANDLER 12
158		159
159	/* TT = 0x4d, TL = 0, interrupt_level_13 handler */	160	/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
160	.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE	161	.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
161	.global interrupt_level_13_handler	162	.global interrupt_level_13_handler
162	interrupt_level_13_handler:	163	interrupt_level_13_handler:
163	INTERRUPT_LEVEL_N_HANDLER 13	164	INTERRUPT_LEVEL_N_HANDLER 13
164		165
165	/* TT = 0x4e, TL = 0, interrupt_level_14 handler */	166	/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
166	.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE	167	.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
167	.global interrupt_level_14_handler	168	.global interrupt_level_14_handler
168	interrupt_level_14_handler:	169	interrupt_level_14_handler:
169	INTERRUPT_LEVEL_N_HANDLER 14	170	INTERRUPT_LEVEL_N_HANDLER 14
170		171
171	/* TT = 0x4f, TL = 0, interrupt_level_15 handler */	172	/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
172	.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE	173	.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
173	.global interrupt_level_15_handler	174	.global interrupt_level_15_handler
174	interrupt_level_15_handler:	175	interrupt_level_15_handler:
175	INTERRUPT_LEVEL_N_HANDLER 15	176	INTERRUPT_LEVEL_N_HANDLER 15
176		177
177	/* TT = 0x60, TL = 0, interrupt_vector_trap handler */	178	/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
178	.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE	179	.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
179	.global interrupt_vector_trap_handler	180	.global interrupt_vector_trap_handler
180	interrupt_vector_trap_handler:	181	interrupt_vector_trap_handler:
181	INTERRUPT_VECTOR_TRAP_HANDLER	182	INTERRUPT_VECTOR_TRAP_HANDLER
182		183
183	/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */	184	/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
184	.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE	185	.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
185	.global fast_instruction_access_mmu_miss_handler	186	.global fast_instruction_access_mmu_miss_handler
186	fast_instruction_access_mmu_miss_handler:	187	fast_instruction_access_mmu_miss_handler:
187	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER	188	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
188		189
189	/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */	190	/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
190	.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE	191	.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
191	.global fast_data_access_mmu_miss_handler	192	.global fast_data_access_mmu_miss_handler
192	fast_data_access_mmu_miss_handler:	193	fast_data_access_mmu_miss_handler:
193	FAST_DATA_ACCESS_MMU_MISS_HANDLER	194	FAST_DATA_ACCESS_MMU_MISS_HANDLER
194		195
195	/* TT = 0x6c, TL = 0, fast_data_access_protection */	196	/* TT = 0x6c, TL = 0, fast_data_access_protection */
196	.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE	197	.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
197	.global fast_data_access_protection_handler	198	.global fast_data_access_protection_handler
198	fast_data_access_protection_handler:	199	fast_data_access_protection_handler:
199	FAST_DATA_ACCESS_PROTECTION_HANDLER	200	FAST_DATA_ACCESS_PROTECTION_HANDLER
200		201
201	/* TT = 0x80, TL = 0, spill_0_normal handler */	202	/* TT = 0x80, TL = 0, spill_0_normal handler */
202	.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE	203	.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
203	.global spill_0_normal	204	.global spill_0_normal
204	spill_0_normal:	205	spill_0_normal:
205	SPILL_NORMAL_HANDLER	206	SPILL_NORMAL_HANDLER
206		207
207	/* TT = 0xc0, TL = 0, fill_0_normal handler */	208	/* TT = 0xc0, TL = 0, fill_0_normal handler */
208	.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE	209	.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
209	.global fill_0_normal	210	.global fill_0_normal
210	fill_0_normal:	211	fill_0_normal:
211	FILL_NORMAL_HANDLER	212	FILL_NORMAL_HANDLER
212		213
213	/*	214	/*
214	* Handlers for TL>0.	215	* Handlers for TL>0.
215	*/	216	*/
216		217
217	/* TT = 0x08, TL > 0, instruction_access_exception */	218	/* TT = 0x08, TL > 0, instruction_access_exception */
218	.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE	219	.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
219	.global instruction_access_exception_high	220	.global instruction_access_exception_high
220	instruction_access_exception_high:	221	instruction_access_exception_high:
221	SIMPLE_HANDLER do_instruction_access_exc	222	SIMPLE_HANDLER do_instruction_access_exc
222		223
223	/* TT = 0x10, TL > 0, illegal_instruction */	224	/* TT = 0x10, TL > 0, illegal_instruction */
224	.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE	225	.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
225	.global illegal_instruction_high	226	.global illegal_instruction_high
226	illegal_instruction_high:	227	illegal_instruction_high:
227	SIMPLE_HANDLER do_illegal_instruction	228	SIMPLE_HANDLER do_illegal_instruction
228		229
229	/* TT = 0x24, TL > 0, clean_window handler */	230	/* TT = 0x24, TL > 0, clean_window handler */
230	.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE	231	.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
231	.global clean_window_handler_high	232	.global clean_window_handler_high
232	clean_window_handler_high:	233	clean_window_handler_high:
233	CLEAN_WINDOW_HANDLER	234	CLEAN_WINDOW_HANDLER
234		235
235	/* TT = 0x32, TL > 0, data_access_error */	236	/* TT = 0x32, TL > 0, data_access_error */
236	.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE	237	.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
237	.global data_access_error_high	238	.global data_access_error_high
238	data_access_error_high:	239	data_access_error_high:
239	SIMPLE_HANDLER do_data_access_error	240	SIMPLE_HANDLER do_data_access_error
240		241
241	/* TT = 0x34, TL > 0, mem_address_not_aligned */	242	/* TT = 0x34, TL > 0, mem_address_not_aligned */
242	.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE	243	.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
243	.global mem_address_not_aligned_high	244	.global mem_address_not_aligned_high
244	mem_address_not_aligned_high:	245	mem_address_not_aligned_high:
245	SIMPLE_HANDLER do_mem_address_not_aligned	246	SIMPLE_HANDLER do_mem_address_not_aligned
246		247
247	/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */	248	/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
248	.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE	249	.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
249	.global fast_instruction_access_mmu_miss_handler_high	250	.global fast_instruction_access_mmu_miss_handler_high
250	fast_instruction_access_mmu_miss_handler_high:	251	fast_instruction_access_mmu_miss_handler_high:
251	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER	252	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
252		253
253	/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */	254	/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
254	.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE	255	.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
255	.global fast_data_access_mmu_miss_handler_high	256	.global fast_data_access_mmu_miss_handler_high
256	fast_data_access_mmu_miss_handler_high:	257	fast_data_access_mmu_miss_handler_high:
257	FAST_DATA_ACCESS_MMU_MISS_HANDLER	258	FAST_DATA_ACCESS_MMU_MISS_HANDLER
258		259
259	/* TT = 0x6c, TL > 0, fast_data_access_protection */	260	/* TT = 0x6c, TL > 0, fast_data_access_protection */
260	.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE	261	.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
261	.global fast_data_access_protection_handler_high	262	.global fast_data_access_protection_handler_high
262	fast_data_access_protection_handler_high:	263	fast_data_access_protection_handler_high:
263	FAST_DATA_ACCESS_PROTECTION_HANDLER	264	FAST_DATA_ACCESS_PROTECTION_HANDLER
264		265
265	/* TT = 0x80, TL > 0, spill_0_normal handler */	266	/* TT = 0x80, TL > 0, spill_0_normal handler */
266	.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE	267	.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
267	.global spill_0_normal_high	268	.global spill_0_normal_high
268	spill_0_normal_high:	269	spill_0_normal_high:
269	SPILL_NORMAL_HANDLER	270	SPILL_NORMAL_HANDLER
270		271
271	/* TT = 0xc0, TL > 0, fill_0_normal handler */	272	/* TT = 0xc0, TL > 0, fill_0_normal handler */
272	.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE	273	.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
273	.global fill_0_normal_high	274	.global fill_0_normal_high
274	fill_0_normal_high:	275	fill_0_normal_high:
275	FILL_NORMAL_HANDLER	276	FILL_NORMAL_HANDLER
276		277
277		278
278	/* Preemptible trap handler.	279	/* Preemptible trap handler for TL=1.
279	*	280	*
280	* This trap handler makes arrangements to	281	* This trap handler makes arrangements to make calling of scheduler() from
-		282	* within a trap context possible. It is guaranteed to function only when traps
281	* make calling scheduler() possible.	283	* are not nested (i.e. for TL=1).
282	*	284	*
-		285	* Every trap handler on TL=1 that makes a call to the scheduler needs to
-		286	* be based on this function. The reason behind it is that the nested
-		287	* trap levels and the automatic saving of the interrupted context by hardware
-		288	* does not work well together with scheduling (i.e. a thread cannot be rescheduled
-		289	* with TL>0). Therefore it is necessary to eliminate the effect of trap levels
-		290	* by software and save the necessary state on the kernel stack.
-		291	*
-		292	* Note that for traps with TL>1, more state needs to be saved. This function
-		293	* is therefore not going to work when TL>1.
-		294	*
283	* The caller is responsible for doing save	295	* The caller is responsible for doing SAVE and allocating
284	* and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE	296	* PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE bytes on the stack.
285	* bytes on stack.	-
286	*	297	*
287	* Input registers:	298	* Input registers:
288	* %l0 Address of function to call.	299	* %l0 Address of function to call.
289	* Output registers:	300	* Output registers:
290	* %l1 - %l7 Copy of %g1 - %g7	301	* %l1 - %l7 Copy of %g1 - %g7
291	*/	302	*/
292	.global preemptible_handler	303	.global preemptible_handler
293	preemptible_handler:	304	preemptible_handler:
294	/*	305	/*
295	* Save TSTATE, TPC, TNPC and PSTATE aside.	306	* Save TSTATE, TPC, TNPC and PSTATE aside.
296	*/	307	*/
297	rdpr %tstate, %g1	308	rdpr %tstate, %g1
298	rdpr %tpc, %g2	309	rdpr %tpc, %g2
299	rdpr %tnpc, %g3	310	rdpr %tnpc, %g3
300	rdpr %pstate, %g4	311	rdpr %pstate, %g4
301		312
-		313	/*
-		314	* The following memory accesses will not fault
-		315	* because special provisions are made to have
-		316	* the kernel stack of THREAD locked in DTLB.
-		317	*/
302	stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]	318	stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
303	stx %g2, [%fp + STACK_BIAS + SAVED_TPC]	319	stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
304	stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]	320	stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]
305	stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]	321	stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]
306		322
307	/*	323	/*
308	* Write 0 to TL.	324	* Write 0 to TL.
309	*/	325	*/
310	wrpr %g0, 0, %tl	326	wrpr %g0, 0, %tl
311		327
312	/*	328	/*
313	* Alter PSTATE.	329	* Alter PSTATE.
314	* - switch to normal globals.	330	* - switch to normal globals.
315	*/	331	*/
316	and %g4, ~1, %g4 ! mask alternate globals	332	and %g4, ~(PSTATE_AG_BIT\|PSTATE_IG_BIT\|PSTATE_MG_BIT), %g4
317	wrpr %g4, 0, %pstate	333	wrpr %g4, 0, %pstate
318		334
319	/*	335	/*
320	* Save the normal globals.	336	* Save the normal globals.
321	*/	337	*/
322	SAVE_GLOBALS	338	SAVE_GLOBALS
323		339
324	/*	340	/*
325	* Call the higher-level handler.	341	* Call the higher-level handler.
326	*/	342	*/
-		343	mov %fp, %o1 ! calculate istate address
327	call %l0	344	call %l0
328	nop	-
-		345	add %o1, STACK_BIAS + SAVED_PSTATE, %o1 ! calculate istate address
329		346
330	/*	347	/*
331	* Restore the normal global register set.	348	* Restore the normal global register set.
332	*/	349	*/
333	RESTORE_GLOBALS	350	RESTORE_GLOBALS
334		351
335	/*	352	/*
336	* Restore PSTATE from saved copy.	353	* Restore PSTATE from saved copy.
337	* Alternate globals become active.	354	* Alternate/Interrupt/MM globals become active.
338	*/	355	*/
339	ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4	356	ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
340	wrpr %l4, 0, %pstate	357	wrpr %l4, 0, %pstate
341		358
342	/*	359	/*
343	* Write 1 to TL.	360	* Write 1 to TL.
344	*/	361	*/
345	wrpr %g0, 1, %tl	362	wrpr %g0, 1, %tl
346		363
347	/*	364	/*
348	* Read TSTATE, TPC and TNPC from saved copy.	365	* Read TSTATE, TPC and TNPC from saved copy.
349	*/	366	*/
350	ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1	367	ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1
351	ldx [%fp + STACK_BIAS + SAVED_TPC], %g2	368	ldx [%fp + STACK_BIAS + SAVED_TPC], %g2
352	ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3	369	ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3
353		370
354	/*	371	/*
355	* Do restore to match the save instruction from the top-level handler.	372	* Do restore to match the save instruction from the top-level handler.
356	*/	373	*/
357	restore	374	restore
358		375
359	/*	376	/*
360	* On execution of retry instruction, CWP will be restored from TSTATE register.	377	* On execution of the RETRY instruction, CWP will be restored from the TSTATE
361	* However, because of scheduling, it is possible that CWP in saved TSTATE	378	* register. However, because of scheduling, it is possible that CWP in the saved
362	* is different from current CWP. The following chunk of code fixes CWP	379	* TSTATE is different from the current CWP. The following chunk of code fixes
363	* in the saved copy of TSTATE.	380	* CWP in the saved copy of TSTATE.
364	*/	381	*/
365	rdpr %cwp, %g4 ! read current CWP	382	rdpr %cwp, %g4 ! read current CWP
366	and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE	383	and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE
367	or %g1, %g4, %g1 ! write current CWP to TSTATE	384	or %g1, %g4, %g1 ! write current CWP to TSTATE
368		385
369	/*	386	/*
370	* Restore TSTATE, TPC and TNPC from saved copies.	387	* Restore TSTATE, TPC and TNPC from saved copies.
371	*/	388	*/
372	wrpr %g1, 0, %tstate	389	wrpr %g1, 0, %tstate
373	wrpr %g2, 0, %tpc	390	wrpr %g2, 0, %tpc
374	wrpr %g3, 0, %tnpc	391	wrpr %g3, 0, %tnpc
375		392
376	/*	393	/*
377	* Return from interrupt.	394	* Return from interrupt.
378	*/	395	*/
379	retry	396	retry
380		397

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(root)/trunk/kernel/arch/sparc64/src/trap/trap_table.S – Rev 1787 → 1851