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/*
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/*
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 * Copyright (C) 2005 Jakub Jermar
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 * Copyright (C) 2005 Jakub Jermar
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup sparc64interrupt
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/** @addtogroup sparc64interrupt
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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#include <arch/trap/interrupt.h>
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#include <interrupt.h>
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#include <interrupt.h>
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#include <arch/drivers/fhc.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <debug.h>
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#include <debug.h>
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#include <ipc/sysipc.h>
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#include <ipc/sysipc.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <genarch/kbd/z8530.h>
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/** Register Interrupt Level Handler.
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/** Register Interrupt Level Handler.
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 *
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 *
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 * @param n Interrupt Level (1 - 15).
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 * @param n Interrupt Level (1 - 15).
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 * @param name Short descriptive string.
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 * @param name Short descriptive string.
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 * @param f Handler.
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 * @param f Handler.
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 */
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 */
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void interrupt_register(int n, const char *name, iroutine f)
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void interrupt_register(int n, const char *name, iroutine f)
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{
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{
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    ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
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    ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
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    exc_register(n - 1, name, f);
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    exc_register(n - 1, name, f);
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}
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}
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/* Reregister irq to be IPC-ready */
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/* Reregister irq to be IPC-ready */
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void irq_ipc_bind_arch(unative_t irq)
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void irq_ipc_bind_arch(unative_t irq)
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{
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{
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    panic("not implemented\n");
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    panic("not implemented\n");
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    /* TODO */
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    /* TODO */
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}
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}
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void interrupt(void)
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{
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    uint64_t intrcv;
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    uint64_t data0;
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    intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
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    data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
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    switch (data0) {
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#ifdef CONFIG_Z8530
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    case Z8530_INTRCV_DATA0:
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        /*
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         * So far, we know we got this interrupt through the FHC.
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         * Since we don't have enough information about the FHC and
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         * because the interrupt looks like level sensitive,
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         * we cannot handle it by scheduling one of the level
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         * interrupt traps. Call the interrupt handler directly.
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         */
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        fhc_uart_reset();
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        z8530_interrupt();
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        break;
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#endif
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    }
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    membar();
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    asi_u64_write(ASI_INTR_RECEIVE, 0, 0);
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}
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/** @}
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/** @}
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 */
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 */
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 - 
 
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