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#
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#
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# Copyright (c) 2005 Jakub Jermar
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# Copyright (c) 2005 Jakub Jermar
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
17
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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28
 
29
#include <arch/arch.h>
29
#include <arch/arch.h>
30
#include <arch/cpu.h>
30
#include <arch/cpu.h>
31
#include <arch/regdef.h>
31
#include <arch/regdef.h>
32
#include <arch/boot/boot.h>
32
#include <arch/boot/boot.h>
33
#include <arch/stack.h>
33
#include <arch/stack.h>
34
 
34
 
35
#include <arch/mm/mmu.h>
35
#include <arch/mm/mmu.h>
36
#include <arch/mm/tlb.h>
36
#include <arch/mm/tlb.h>
37
#include <arch/mm/tte.h>
37
#include <arch/mm/tte.h>
38
 
38
 
39
#ifdef CONFIG_SMP
39
#ifdef CONFIG_SMP
40
#include <arch/context_offset.h>
40
#include <arch/context_offset.h>
41
#endif
41
#endif
42
 
42
 
43
.register %g2, #scratch
43
.register %g2, #scratch
44
.register %g3, #scratch
44
.register %g3, #scratch
45
 
45
 
46
.section K_TEXT_START, "ax"
46
.section K_TEXT_START, "ax"
47
 
47
 
48
#define BSP_FLAG	1
48
#define BSP_FLAG	1
49
 
49
 
50
/*
50
/*
51
 * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
51
 * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
52
 * a given processor.
52
 * a given processor.
53
 */
53
 */
54
#if defined (US)
54
#if defined (US)
55
    #define PHYSMEM_ADDR_SIZE	41
55
    #define PHYSMEM_ADDR_SIZE	41
56
#elif defined (US3)
56
#elif defined (US3)
57
    #define PHYSMEM_ADDR_SIZE	43
57
    #define PHYSMEM_ADDR_SIZE	43
58
#endif
58
#endif
59
 
59
 
60
/*
60
/*
61
 * Here is where the kernel is passed control from the boot loader.
61
 * Here is where the kernel is passed control from the boot loader.
62
 * 
62
 * 
63
 * The registers are expected to be in this state:
63
 * The registers are expected to be in this state:
64
 * - %o0 starting address of physical memory + bootstrap processor flag
64
 * - %o0 starting address of physical memory + bootstrap processor flag
65
 * 	bits 63...1:	physical memory starting address / 2
65
 * 	bits 63...1:	physical memory starting address / 2
66
 *	bit 0:		non-zero on BSP processor, zero on AP processors
66
 *	bit 0:		non-zero on BSP processor, zero on AP processors
67
 * - %o1 bootinfo structure address (BSP only)
67
 * - %o1 bootinfo structure address (BSP only)
68
 * - %o2 bootinfo structure size (BSP only)
68
 * - %o2 bootinfo structure size (BSP only)
69
 *
69
 *
70
 * Moreover, we depend on boot having established the following environment:
70
 * Moreover, we depend on boot having established the following environment:
71
 * - TLBs are on
71
 * - TLBs are on
72
 * - identity mapping for the kernel image
72
 * - identity mapping for the kernel image
73
 */
73
 */
74
 
74
 
75
.global kernel_image_start
75
.global kernel_image_start
76
kernel_image_start:
76
kernel_image_start:
77
	mov BSP_FLAG, %l0
77
	mov BSP_FLAG, %l0
78
	and %o0, %l0, %l7			! l7 <= bootstrap processor?
78
	and %o0, %l0, %l7			! l7 <= bootstrap processor?
79
	andn %o0, %l0, %l6			! l6 <= start of physical memory
79
	andn %o0, %l0, %l6			! l6 <= start of physical memory
80
 
80
 
81
	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
81
	! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
82
	srlx %l6, 13, %l5
82
	srlx %l6, 13, %l5
83
	
83
	
84
	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
84
	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
85
	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
85
	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
86
	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
86
	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
87
 
87
 
88
	/*
88
	/*
89
	 * Setup basic runtime environment.
89
	 * Setup basic runtime environment.
90
	 */
90
	 */
91
 
91
 
92
	wrpr %g0, NWINDOWS - 2, %cansave	! set maximum saveable windows
92
	wrpr %g0, NWINDOWS - 2, %cansave	! set maximum saveable windows
93
	wrpr %g0, 0, %canrestore		! get rid of windows we will
93
	wrpr %g0, 0, %canrestore		! get rid of windows we will
94
						! never need again
94
						! never need again
95
	wrpr %g0, 0, %otherwin			! make sure the window state is
95
	wrpr %g0, 0, %otherwin			! make sure the window state is
96
						! consistent
96
						! consistent
97
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
97
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window
98
						! traps for kernel
98
						! traps for kernel
99
						
99
						
100
	wrpr %g0, 0, %wstate			! use default spill/fill trap
100
	wrpr %g0, 0, %wstate			! use default spill/fill trap
101
 
101
 
102
	wrpr %g0, 0, %tl			! TL = 0, primary context
102
	wrpr %g0, 0, %tl			! TL = 0, primary context
103
						! register is used
103
						! register is used
104
 
104
 
105
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
105
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! disable interrupts and disable
106
						! 32-bit address masking
106
						! 32-bit address masking
107
 
107
 
108
	wrpr %g0, 0, %pil			! intialize %pil
108
	wrpr %g0, 0, %pil			! intialize %pil
109
 
109
 
110
	/*
110
	/*
111
	 * Switch to kernel trap table.
111
	 * Switch to kernel trap table.
112
	 */
112
	 */
113
	sethi %hi(trap_table), %g1
113
	sethi %hi(trap_table), %g1
114
	wrpr %g1, %lo(trap_table), %tba
114
	wrpr %g1, %lo(trap_table), %tba
115
 
115
 
116
	/* 
116
	/* 
117
	 * Take over the DMMU by installing locked TTE entry identically
117
	 * Take over the DMMU by installing locked TTE entry identically
118
	 * mapping the first 4M of memory.
118
	 * mapping the first 4M of memory.
119
	 *
119
	 *
120
	 * In case of DMMU, no FLUSH instructions need to be issued. Because of
120
	 * In case of DMMU, no FLUSH instructions need to be issued. Because of
121
	 * that, the old DTLB contents can be demapped pretty straightforwardly
121
	 * that, the old DTLB contents can be demapped pretty straightforwardly
122
	 * and without causing any traps.
122
	 * and without causing any traps.
123
	 */
123
	 */
124
 
124
 
125
	wr %g0, ASI_DMMU, %asi
125
	wr %g0, ASI_DMMU, %asi
126
 
126
 
127
#define SET_TLB_DEMAP_CMD(r1, context_id) \
127
#define SET_TLB_DEMAP_CMD(r1, context_id) \
128
	set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
128
	set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
129
		TLB_DEMAP_CONTEXT_SHIFT), %r1
129
		TLB_DEMAP_CONTEXT_SHIFT), %r1
130
	
130
	
131
	! demap context 0
131
	! demap context 0
132
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
132
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
133
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
133
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
134
	membar #Sync
134
	membar #Sync
135
 
135
 
136
#define SET_TLB_TAG(r1, context) \
136
#define SET_TLB_TAG(r1, context) \
137
	set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
137
	set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
138
 
138
 
139
	! write DTLB tag
139
	! write DTLB tag
140
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
140
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
141
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
141
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
142
	membar #Sync
142
	membar #Sync
143
 
143
 
144
#ifdef CONFIG_VIRT_IDX_DCACHE
144
#ifdef CONFIG_VIRT_IDX_DCACHE
145
#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_CV | TTE_P | LMA | (imm))
145
#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_CV | TTE_P | LMA | (imm))
146
#else /* CONFIG_VIRT_IDX_DCACHE */
146
#else /* CONFIG_VIRT_IDX_DCACHE */
147
#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_P | LMA | (imm))
147
#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_P | LMA | (imm))
148
#endif /* CONFIG_VIRT_IDX_DCACHE */
148
#endif /* CONFIG_VIRT_IDX_DCACHE */
149
 
149
 
150
#define SET_TLB_DATA(r1, r2, imm) \
150
#define SET_TLB_DATA(r1, r2, imm) \
151
	set TTE_LOW_DATA(imm), %r1; \
151
	set TTE_LOW_DATA(imm), %r1; \
152
	or %r1, %l5, %r1; \
152
	or %r1, %l5, %r1; \
153
	mov PAGESIZE_4M, %r2; \
153
	mov PAGESIZE_4M, %r2; \
154
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
154
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
155
	or %r1, %r2, %r1; \
155
	or %r1, %r2, %r1; \
156
	mov 1, %r2; \
156
	mov 1, %r2; \
157
	sllx %r2, TTE_V_SHIFT, %r2; \
157
	sllx %r2, TTE_V_SHIFT, %r2; \
158
	or %r1, %r2, %r1;
158
	or %r1, %r2, %r1;
159
	
159
	
160
	! write DTLB data and install the kernel mapping
160
	! write DTLB data and install the kernel mapping
161
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
161
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
162
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
162
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
163
	membar #Sync
163
	membar #Sync
164
 
164
 
165
	/*
165
	/*
166
	 * Because we cannot use global mappings (because we want to have
166
	 * Because we cannot use global mappings (because we want to have
167
	 * separate 64-bit address spaces for both the kernel and the
167
	 * separate 64-bit address spaces for both the kernel and the
168
	 * userspace), we prepare the identity mapping also in context 1. This
168
	 * userspace), we prepare the identity mapping also in context 1. This
169
	 * step is required by the code installing the ITLB mapping.
169
	 * step is required by the code installing the ITLB mapping.
170
	 */
170
	 */
171
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
171
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
172
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
172
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
173
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
173
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
174
	membar #Sync
174
	membar #Sync
175
 
175
 
176
	! write DTLB data and install the kernel mapping in context 1
176
	! write DTLB data and install the kernel mapping in context 1
177
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
177
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
178
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
178
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
179
	membar #Sync
179
	membar #Sync
180
	
180
	
181
	/*
181
	/*
182
	 * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
182
	 * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
183
	 * as easily as the DMMU, because the IMMU is mapping the code it
183
	 * as easily as the DMMU, because the IMMU is mapping the code it
184
	 * executes.
184
	 * executes.
185
	 *
185
	 *
186
	 * [ Note that brave experiments with disabling the IMMU and using the
186
	 * [ Note that brave experiments with disabling the IMMU and using the
187
	 * DMMU approach failed after a dozen of desparate days with only little
187
	 * DMMU approach failed after a dozen of desparate days with only little
188
	 * success. ]
188
	 * success. ]
189
	 *
189
	 *
190
	 * The approach used here is inspired from OpenBSD. First, the kernel
190
	 * The approach used here is inspired from OpenBSD. First, the kernel
191
	 * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and
191
	 * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and
192
	 * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
192
	 * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
193
	 * afterwards and replaced with the kernel permanent mapping. Finally,
193
	 * afterwards and replaced with the kernel permanent mapping. Finally,
194
	 * the kernel switches back to context 0 and demaps context 1.
194
	 * the kernel switches back to context 0 and demaps context 1.
195
	 *
195
	 *
196
	 * Moreover, the IMMU requires use of the FLUSH instructions. But that
196
	 * Moreover, the IMMU requires use of the FLUSH instructions. But that
197
	 * is OK because we always use operands with addresses already mapped by
197
	 * is OK because we always use operands with addresses already mapped by
198
	 * the taken over DTLB.
198
	 * the taken over DTLB.
199
	 */
199
	 */
200
	
200
	
201
	set kernel_image_start, %g5
201
	set kernel_image_start, %g5
202
	
202
	
203
	! write ITLB tag of context 1
203
	! write ITLB tag of context 1
204
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
204
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
205
	mov VA_DMMU_TAG_ACCESS, %g2
205
	mov VA_DMMU_TAG_ACCESS, %g2
206
	stxa %g1, [%g2] ASI_IMMU
206
	stxa %g1, [%g2] ASI_IMMU
207
	flush %g5
207
	flush %g5
208
 
208
 
209
	! write ITLB data and install the temporary mapping in context 1
209
	! write ITLB data and install the temporary mapping in context 1
210
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
210
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
211
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
211
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
212
	flush %g5
212
	flush %g5
213
	
213
	
214
	! switch to context 1
214
	! switch to context 1
215
	mov MEM_CONTEXT_TEMP, %g1
215
	mov MEM_CONTEXT_TEMP, %g1
216
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
216
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
217
	flush %g5
217
	flush %g5
218
	
218
	
219
	! demap context 0
219
	! demap context 0
220
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
220
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
221
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
221
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
222
	flush %g5
222
	flush %g5
223
	
223
	
224
	! write ITLB tag of context 0
224
	! write ITLB tag of context 0
225
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
225
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
226
	mov VA_DMMU_TAG_ACCESS, %g2
226
	mov VA_DMMU_TAG_ACCESS, %g2
227
	stxa %g1, [%g2] ASI_IMMU
227
	stxa %g1, [%g2] ASI_IMMU
228
	flush %g5
228
	flush %g5
229
 
229
 
230
	! write ITLB data and install the permanent kernel mapping in context 0
230
	! write ITLB data and install the permanent kernel mapping in context 0
231
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
231
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
232
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
232
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
233
	flush %g5
233
	flush %g5
234
 
234
 
235
	! enter nucleus - using context 0
235
	! enter nucleus - using context 0
236
	wrpr %g0, 1, %tl
236
	wrpr %g0, 1, %tl
237
 
237
 
238
	! demap context 1
238
	! demap context 1
239
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
239
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
240
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
240
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
241
	flush %g5
241
	flush %g5
242
	
242
	
243
	! set context 0 in the primary context register
243
	! set context 0 in the primary context register
244
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
244
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
245
	flush %g5
245
	flush %g5
246
	
246
	
247
	! leave nucleus - using primary context, i.e. context 0
247
	! leave nucleus - using primary context, i.e. context 0
248
	wrpr %g0, 0, %tl
248
	wrpr %g0, 0, %tl
249
 
249
 
250
	brz %l7, 1f				! skip if you are not the bootstrap CPU
250
	brz %l7, 1f				! skip if you are not the bootstrap CPU
251
	nop
251
	nop
252
 
252
 
253
	/*
253
	/*
254
	 * Save physmem_base for use by the mm subsystem.
254
	 * Save physmem_base for use by the mm subsystem.
255
	 * %l6 contains starting physical address
255
	 * %l6 contains starting physical address
256
	 */
256
	 */
257
	sethi %hi(physmem_base), %l4
257
	sethi %hi(physmem_base), %l4
258
	stx %l6, [%l4 + %lo(physmem_base)]
258
	stx %l6, [%l4 + %lo(physmem_base)]
259
 
259
 
260
	/*
260
	/*
261
	 * Precompute kernel 8K TLB data template.
261
	 * Precompute kernel 8K TLB data template.
262
	 * %l5 contains starting physical address
262
	 * %l5 contains starting physical address
263
	 * bits [(PHYSMEM_ADDR_SIZE - 1):13]
263
	 * bits [(PHYSMEM_ADDR_SIZE - 1):13]
264
	 */
264
	 */
265
	sethi %hi(kernel_8k_tlb_data_template), %l4
265
	sethi %hi(kernel_8k_tlb_data_template), %l4
266
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
266
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
267
	or %l3, %l5, %l3
267
	or %l3, %l5, %l3
268
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
268
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
269
 
269
 
270
	/*
270
	/*
271
	 * Flush D-Cache.
271
	 * Flush D-Cache.
272
	 */
272
	 */
273
	call dcache_flush
273
	call dcache_flush
274
	nop
274
	nop
275
 
275
 
276
	/*
276
	/*
277
	 * So far, we have not touched the stack.
277
	 * So far, we have not touched the stack.
278
	 * It is a good idea to set the kernel stack to a known state now.
278
	 * It is a good idea to set the kernel stack to a known state now.
279
	 */
279
	 */
280
	sethi %hi(temporary_boot_stack), %sp
280
	sethi %hi(temporary_boot_stack), %sp
281
	or %sp, %lo(temporary_boot_stack), %sp
281
	or %sp, %lo(temporary_boot_stack), %sp
282
	sub %sp, STACK_BIAS, %sp
282
	sub %sp, STACK_BIAS, %sp
283
 
283
 
284
	sethi %hi(bootinfo), %o0
284
	sethi %hi(bootinfo), %o0
285
	call memcpy				! copy bootinfo
285
	call memcpy				! copy bootinfo
286
	or %o0, %lo(bootinfo), %o0
286
	or %o0, %lo(bootinfo), %o0
287
 
287
 
288
	call arch_pre_main
288
	call arch_pre_main
289
	nop
289
	nop
290
	
290
	
291
	call main_bsp
291
	call main_bsp
292
	nop
292
	nop
293
 
293
 
294
	/* Not reached. */
294
	/* Not reached. */
295
 
295
 
296
0:
296
0:
297
	ba 0b
297
	ba %xcc, 0b
298
	nop
298
	nop
299
 
299
 
300
 
300
 
301
1:
301
1:
302
#ifdef CONFIG_SMP
302
#ifdef CONFIG_SMP
303
	/*
303
	/*
304
	 * Determine the width of the MID and save its mask to %g3. The width
304
	 * Determine the width of the MID and save its mask to %g3. The width
305
	 * is
305
	 * is
306
	 * 	* 5 for US and US-IIIi,
306
	 * 	* 5 for US and US-IIIi,
307
	 * 	* 10 for US3 except US-IIIi.
307
	 * 	* 10 for US3 except US-IIIi.
308
	 */
308
	 */
309
#if defined(US)
309
#if defined(US)
310
	mov 0x1f, %g3
310
	mov 0x1f, %g3
311
#elif defined(US3)
311
#elif defined(US3)
312
	mov 0x3ff, %g3
312
	mov 0x3ff, %g3
313
	rdpr %ver, %g2
313
	rdpr %ver, %g2
314
	sllx %g2, 16, %g2
314
	sllx %g2, 16, %g2
315
	srlx %g2, 48, %g2
315
	srlx %g2, 48, %g2
316
	cmp %g2, IMPL_ULTRASPARCIII_I
316
	cmp %g2, IMPL_ULTRASPARCIII_I
317
	move %xcc, 0x1f, %g3
317
	move %xcc, 0x1f, %g3
318
#endif
318
#endif
319
 
319
 
320
	/*
320
	/*
321
	 * Read MID from the processor.
321
	 * Read MID from the processor.
322
	 */
322
	 */
323
	ldxa [%g0] ASI_ICBUS_CONFIG, %g1
323
	ldxa [%g0] ASI_ICBUS_CONFIG, %g1
324
	srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
324
	srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
325
	and %g1, %g3, %g1
325
	and %g1, %g3, %g1
326
 
326
 
327
	/*
327
	/*
328
	 * Active loop for APs until the BSP picks them up. A processor cannot
328
	 * Active loop for APs until the BSP picks them up. A processor cannot
329
	 * leave the loop until the global variable 'waking_up_mid' equals its
329
	 * leave the loop until the global variable 'waking_up_mid' equals its
330
	 * MID.
330
	 * MID.
331
	 */
331
	 */
332
	set waking_up_mid, %g2
332
	set waking_up_mid, %g2
333
2:
333
2:
334
	ldx [%g2], %g3
334
	ldx [%g2], %g3
335
	cmp %g3, %g1
335
	cmp %g3, %g1
336
	bne %xcc, 2b
336
	bne %xcc, 2b
337
	nop
337
	nop
338
 
338
 
339
	/*
339
	/*
340
	 * Configure stack for the AP.
340
	 * Configure stack for the AP.
341
	 * The AP is expected to use the stack saved
341
	 * The AP is expected to use the stack saved
342
	 * in the ctx global variable.
342
	 * in the ctx global variable.
343
	 */
343
	 */
344
	set ctx, %g1
344
	set ctx, %g1
345
	add %g1, OFFSET_SP, %g1
345
	add %g1, OFFSET_SP, %g1
346
	ldx [%g1], %o6
346
	ldx [%g1], %o6
347
 
347
 
348
	call main_ap
348
	call main_ap
349
	nop
349
	nop
350
 
350
 
351
	/* Not reached. */
351
	/* Not reached. */
352
#endif
352
#endif
353
	
353
	
354
0:
354
0:
355
	ba 0b
355
	ba %xcc, 0b
356
	nop
356
	nop
357
 
357
 
358
 
358
 
359
.section K_DATA_START, "aw", @progbits
359
.section K_DATA_START, "aw", @progbits
360
 
360
 
361
/*
361
/*
362
 * Create small stack to be used by the bootstrap processor. It is going to be
362
 * Create small stack to be used by the bootstrap processor. It is going to be
363
 * used only for a very limited period of time, but we switch to it anyway,
363
 * used only for a very limited period of time, but we switch to it anyway,
364
 * just to be sure we are properly initialized.
364
 * just to be sure we are properly initialized.
365
 */
365
 */
366
 
366
 
367
#define INITIAL_STACK_SIZE	1024
367
#define INITIAL_STACK_SIZE	1024
368
 
368
 
369
.align STACK_ALIGNMENT
369
.align STACK_ALIGNMENT
370
	.space INITIAL_STACK_SIZE
370
	.space INITIAL_STACK_SIZE
371
.align STACK_ALIGNMENT
371
.align STACK_ALIGNMENT
372
temporary_boot_stack:
372
temporary_boot_stack:
373
	.space STACK_WINDOW_SAVE_AREA_SIZE
373
	.space STACK_WINDOW_SAVE_AREA_SIZE
374
 
374
 
375
 
375
 
376
.data
376
.data
377
 
377
 
378
.align 8
378
.align 8
379
.global physmem_base		! copy of the physical memory base address
379
.global physmem_base		! copy of the physical memory base address
380
physmem_base:
380
physmem_base:
381
	.quad 0
381
	.quad 0
382
 
382
 
383
/*
383
/*
384
 * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and
384
 * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and
385
 * kernel_8k_tlb_data_template variables are meant to stay together,
385
 * kernel_8k_tlb_data_template variables are meant to stay together,
386
 * aligned on 16B boundary.
386
 * aligned on 16B boundary.
387
 */
387
 */
388
.global fast_data_access_mmu_miss_data_hi
388
.global fast_data_access_mmu_miss_data_hi
389
.global end_of_identity 
389
.global end_of_identity 
390
.global kernel_8k_tlb_data_template
390
.global kernel_8k_tlb_data_template
391
 
391
 
392
.align 16
392
.align 16
393
/*
393
/*
394
 * This label is used by the fast_data_access_MMU_miss trap handler.
394
 * This label is used by the fast_data_access_MMU_miss trap handler.
395
 */
395
 */
396
fast_data_access_mmu_miss_data_hi:
396
fast_data_access_mmu_miss_data_hi:
397
/*
397
/*
398
 * This variable is used by the fast_data_access_MMU_miss trap handler.
398
 * This variable is used by the fast_data_access_MMU_miss trap handler.
399
 * In runtime, it is modified to contain the address of the end of physical
399
 * In runtime, it is modified to contain the address of the end of physical
400
 * memory.
400
 * memory.
401
 */
401
 */
402
end_of_identity:
402
end_of_identity:
403
	.quad -1 
403
	.quad -1 
404
/*
404
/*
405
 * This variable is used by the fast_data_access_MMU_miss trap handler.
405
 * This variable is used by the fast_data_access_MMU_miss trap handler.
406
 * In runtime, it is further modified to reflect the starting address of
406
 * In runtime, it is further modified to reflect the starting address of
407
 * physical memory.
407
 * physical memory.
408
 */
408
 */
409
kernel_8k_tlb_data_template:
409
kernel_8k_tlb_data_template:
410
#ifdef CONFIG_VIRT_IDX_DCACHE
410
#ifdef CONFIG_VIRT_IDX_DCACHE
411
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
411
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
412
		 TTE_CV | TTE_P | TTE_W)
412
		 TTE_CV | TTE_P | TTE_W)
413
#else /* CONFIG_VIRT_IDX_DCACHE */
413
#else /* CONFIG_VIRT_IDX_DCACHE */
414
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
414
	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
415
		TTE_P | TTE_W)
415
		TTE_P | TTE_W)
416
#endif /* CONFIG_VIRT_IDX_DCACHE */
416
#endif /* CONFIG_VIRT_IDX_DCACHE */
417
 
417
 
418
 
418