WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/regdef.h>
#include <arch/boot/boot.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
/*
 * Here is where the kernel is passed control
 * from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 non-zero for the bootstrup processor, zero for application/secondary processors
 * - %o1 bootinfo structure address
 * - %o2 bootinfo structure size
 *
 * Moreover, we depend on boot having established the
 * following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 * - identity mapping for memory stack
 */
 
.global kernel_image_start
kernel_image_start:
	brz %o0, kernel_image_start		! block secondary processors
	nop
 
	/*
	 * Setup basic runtime environment.
	 */
 
	flushw					! flush all but the active register window
 
	wrpr %g0, 0, %tl			! TL = 0, primary context register is used
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! Disable interrupts and disable 32-bit address masking.
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Copy the bootinfo structure passed from the boot loader
	 * to the kernel bootinfo structure.
	 */
 
 
	sethi %hi(bootinfo), %o0
	call memcpy
	or %o0, %lo(bootinfo), %o0
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
	set PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	mov 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
 
	/*
	 * Because we cannot use global mappings (because we want to
	 * have separate 64-bit address spaces for both the kernel
	 * and the userspace), we prepare the identity mapping also in
	 * context 1. This step is required by the
	 * code installing the ITLB mapping.
	 */
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
	! write DTLB data and install the kernel mapping in context 1
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! switch to context 0
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! ensure nucleus mapping
	wrpr %g0, 1, %tl
 
	! set context 1 in the primary context register
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! set TL back to 0
	wrpr %g0, 0, %tl
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
2:
	b 2b
	nop
 

Rev 1887	Rev 1899
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/regdef.h>	29	#include <arch/regdef.h>
30	#include <arch/boot/boot.h>	30	#include <arch/boot/boot.h>
31		31
32	#include <arch/mm/mmu.h>	32	#include <arch/mm/mmu.h>
33	#include <arch/mm/tlb.h>	33	#include <arch/mm/tlb.h>
34	#include <arch/mm/tte.h>	34	#include <arch/mm/tte.h>
35		35
36	.register %g2, #scratch	36	.register %g2, #scratch
37	.register %g3, #scratch	37	.register %g3, #scratch
38		38
39	.section K_TEXT_START, "ax"	39	.section K_TEXT_START, "ax"
40		40
41	/*	41	/*
42	* Here is where the kernel is passed control	42	* Here is where the kernel is passed control
43	* from the boot loader.	43	* from the boot loader.
44	*	44	*
45	* The registers are expected to be in this state:	45	* The registers are expected to be in this state:
-		46	* - %o0 non-zero for the bootstrup processor, zero for application/secondary processors
46	* - %o0 bootinfo structure address	47	* - %o1 bootinfo structure address
47	* - %o1 bootinfo structure size	48	* - %o2 bootinfo structure size
48	*	49	*
49	* Moreover, we depend on boot having established the	50	* Moreover, we depend on boot having established the
50	* following environment:	51	* following environment:
51	* - TLBs are on	52	* - TLBs are on
52	* - identity mapping for the kernel image	53	* - identity mapping for the kernel image
53	* - identity mapping for memory stack	54	* - identity mapping for memory stack
54	*/	55	*/
55		56
56	.global kernel_image_start	57	.global kernel_image_start
57	kernel_image_start:	58	kernel_image_start:
-		59	brz %o0, kernel_image_start ! block secondary processors
-		60	nop
58		61
59	/*	62	/*
60	* Setup basic runtime environment.	63	* Setup basic runtime environment.
61	*/	64	*/
62		65
63	flushw ! flush all but the active register window	66	flushw ! flush all but the active register window
64		67
65	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	68	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
66		69
67	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.	70	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
68		71
69	wrpr %g0, 0, %pil ! intialize %pil	72	wrpr %g0, 0, %pil ! intialize %pil
70		73
71	/*	74	/*
72	* Copy the bootinfo structure passed from the boot loader	75	* Copy the bootinfo structure passed from the boot loader
73	* to the kernel bootinfo structure.	76	* to the kernel bootinfo structure.
74	*/	77	*/
75	mov %o1, %o2	-
76	mov %o0, %o1	-
77	sethi %hi(bootinfo), %o0	78	sethi %hi(bootinfo), %o0
78	call memcpy	79	call memcpy
79	or %o0, %lo(bootinfo), %o0	80	or %o0, %lo(bootinfo), %o0
80		81
81	/*	82	/*
82	* Switch to kernel trap table.	83	* Switch to kernel trap table.
83	*/	84	*/
84	sethi %hi(trap_table), %g1	85	sethi %hi(trap_table), %g1
85	wrpr %g1, %lo(trap_table), %tba	86	wrpr %g1, %lo(trap_table), %tba
86		87
87	/*	88	/*
88	* Take over the DMMU by installing global locked	89	* Take over the DMMU by installing global locked
89	* TTE entry identically mapping the first 4M	90	* TTE entry identically mapping the first 4M
90	* of memory.	91	* of memory.
91	*	92	*
92	* In case of DMMU, no FLUSH instructions need to be	93	* In case of DMMU, no FLUSH instructions need to be
93	* issued. Because of that, the old DTLB contents can	94	* issued. Because of that, the old DTLB contents can
94	* be demapped pretty straightforwardly and without	95	* be demapped pretty straightforwardly and without
95	* causing any traps.	96	* causing any traps.
96	*/	97	*/
97		98
98	wr %g0, ASI_DMMU, %asi	99	wr %g0, ASI_DMMU, %asi
99		100
100	#define SET_TLB_DEMAP_CMD(r1, context_id) \	101	#define SET_TLB_DEMAP_CMD(r1, context_id) \
101	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	102	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
102		103
103	! demap context 0	104	! demap context 0
104	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	105	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
105	stxa %g0, [%g1] ASI_DMMU_DEMAP	106	stxa %g0, [%g1] ASI_DMMU_DEMAP
106	membar #Sync	107	membar #Sync
107		108
108	#define SET_TLB_TAG(r1, context) \	109	#define SET_TLB_TAG(r1, context) \
109	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	110	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
110		111
111	! write DTLB tag	112	! write DTLB tag
112	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	113	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
113	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	114	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
114	membar #Sync	115	membar #Sync
115		116
116	#define SET_TLB_DATA(r1, r2, imm) \	117	#define SET_TLB_DATA(r1, r2, imm) \
117	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \	118	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \
118	set PAGESIZE_4M, %r2; \	119	set PAGESIZE_4M, %r2; \
119	sllx %r2, TTE_SIZE_SHIFT, %r2; \	120	sllx %r2, TTE_SIZE_SHIFT, %r2; \
120	or %r1, %r2, %r1; \	121	or %r1, %r2, %r1; \
121	mov 1, %r2; \	122	mov 1, %r2; \
122	sllx %r2, TTE_V_SHIFT, %r2; \	123	sllx %r2, TTE_V_SHIFT, %r2; \
123	or %r1, %r2, %r1;	124	or %r1, %r2, %r1;
124		125
125	! write DTLB data and install the kernel mapping	126	! write DTLB data and install the kernel mapping
126	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping	127	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping
127	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	128	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
128	membar #Sync	129	membar #Sync
129		130
130	/*	131	/*
131	* Because we cannot use global mappings (because we want to	132	* Because we cannot use global mappings (because we want to
132	* have separate 64-bit address spaces for both the kernel	133	* have separate 64-bit address spaces for both the kernel
133	* and the userspace), we prepare the identity mapping also in	134	* and the userspace), we prepare the identity mapping also in
134	* context 1. This step is required by the	135	* context 1. This step is required by the
135	* code installing the ITLB mapping.	136	* code installing the ITLB mapping.
136	*/	137	*/
137	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)	138	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
138	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	139	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
139	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	140	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
140	membar #Sync	141	membar #Sync
141		142
142	! write DTLB data and install the kernel mapping in context 1	143	! write DTLB data and install the kernel mapping in context 1
143	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping	144	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
144	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	145	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
145	membar #Sync	146	membar #Sync
146		147
147	/*	148	/*
148	* Now is time to take over the IMMU.	149	* Now is time to take over the IMMU.
149	* Unfortunatelly, it cannot be done as easily as the DMMU,	150	* Unfortunatelly, it cannot be done as easily as the DMMU,
150	* because the IMMU is mapping the code it executes.	151	* because the IMMU is mapping the code it executes.
151	*	152	*
152	* [ Note that brave experiments with disabling the IMMU	153	* [ Note that brave experiments with disabling the IMMU
153	* and using the DMMU approach failed after a dozen	154	* and using the DMMU approach failed after a dozen
154	* of desparate days with only little success. ]	155	* of desparate days with only little success. ]
155	*	156	*
156	* The approach used here is inspired from OpenBSD.	157	* The approach used here is inspired from OpenBSD.
157	* First, the kernel creates IMMU mapping for itself	158	* First, the kernel creates IMMU mapping for itself
158	* in context 1 (MEM_CONTEXT_TEMP) and switches to	159	* in context 1 (MEM_CONTEXT_TEMP) and switches to
159	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	160	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
160	* afterwards and replaced with the kernel permanent	161	* afterwards and replaced with the kernel permanent
161	* mapping. Finally, the kernel switches back to	162	* mapping. Finally, the kernel switches back to
162	* context 0 and demaps context 1.	163	* context 0 and demaps context 1.
163	*	164	*
164	* Moreover, the IMMU requires use of the FLUSH instructions.	165	* Moreover, the IMMU requires use of the FLUSH instructions.
165	* But that is OK because we always use operands with	166	* But that is OK because we always use operands with
166	* addresses already mapped by the taken over DTLB.	167	* addresses already mapped by the taken over DTLB.
167	*/	168	*/
168		169
169	set kernel_image_start, %g5	170	set kernel_image_start, %g5
170		171
171	! write ITLB tag of context 1	172	! write ITLB tag of context 1
172	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	173	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
173	mov VA_DMMU_TAG_ACCESS, %g2	174	mov VA_DMMU_TAG_ACCESS, %g2
174	stxa %g1, [%g2] ASI_IMMU	175	stxa %g1, [%g2] ASI_IMMU
175	flush %g5	176	flush %g5
176		177
177	! write ITLB data and install the temporary mapping in context 1	178	! write ITLB data and install the temporary mapping in context 1
178	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	179	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
179	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	180	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
180	flush %g5	181	flush %g5
181		182
182	! switch to context 1	183	! switch to context 1
183	mov MEM_CONTEXT_TEMP, %g1	184	mov MEM_CONTEXT_TEMP, %g1
184	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	185	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
185	flush %g5	186	flush %g5
186		187
187	! demap context 0	188	! demap context 0
188	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	189	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
189	stxa %g0, [%g1] ASI_IMMU_DEMAP	190	stxa %g0, [%g1] ASI_IMMU_DEMAP
190	flush %g5	191	flush %g5
191		192
192	! write ITLB tag of context 0	193	! write ITLB tag of context 0
193	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	194	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
194	mov VA_DMMU_TAG_ACCESS, %g2	195	mov VA_DMMU_TAG_ACCESS, %g2
195	stxa %g1, [%g2] ASI_IMMU	196	stxa %g1, [%g2] ASI_IMMU
196	flush %g5	197	flush %g5
197		198
198	! write ITLB data and install the permanent kernel mapping in context 0	199	! write ITLB data and install the permanent kernel mapping in context 0
199	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping	200	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
200	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	201	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
201	flush %g5	202	flush %g5
202		203
203	! switch to context 0	204	! switch to context 0
204	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	205	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
205	flush %g5	206	flush %g5
206		207
207	! ensure nucleus mapping	208	! ensure nucleus mapping
208	wrpr %g0, 1, %tl	209	wrpr %g0, 1, %tl
209		210
210	! set context 1 in the primary context register	211	! set context 1 in the primary context register
211	mov MEM_CONTEXT_TEMP, %g1	212	mov MEM_CONTEXT_TEMP, %g1
212	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	213	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
213	flush %g5	214	flush %g5
214		215
215	! demap context 1	216	! demap context 1
216	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	217	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
217	stxa %g0, [%g1] ASI_IMMU_DEMAP	218	stxa %g0, [%g1] ASI_IMMU_DEMAP
218	flush %g5	219	flush %g5
219		220
220	! set context 0 in the primary context register	221	! set context 0 in the primary context register
221	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	222	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
222	flush %g5	223	flush %g5
223		224
224	! set TL back to 0	225	! set TL back to 0
225	wrpr %g0, 0, %tl	226	wrpr %g0, 0, %tl
226		227
227	call arch_pre_main	228	call arch_pre_main
228	nop	229	nop
229		230
230	call main_bsp	231	call main_bsp
231	nop	232	nop
232		233
233	/* Not reached. */	234	/* Not reached. */
234		235
235	2:	236	2:
236	b 2b	237	b 2b
237	nop	238	nop
238		239

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(root)/trunk/kernel/arch/sparc64/src/start.S @ 3141 – Rev 1887 → 1899