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1 | # |
1 | # |
2 | # Copyright (C) 2005 Jakub Jermar |
2 | # Copyright (C) 2005 Jakub Jermar |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include <arch/regdef.h> |
29 | #include <arch/regdef.h> |
30 | #include <arch/boot/boot.h> |
30 | #include <arch/boot/boot.h> |
31 | 31 | ||
32 | #include <arch/mm/mmu.h> |
32 | #include <arch/mm/mmu.h> |
33 | #include <arch/mm/tlb.h> |
33 | #include <arch/mm/tlb.h> |
34 | #include <arch/mm/tte.h> |
34 | #include <arch/mm/tte.h> |
35 | 35 | ||
36 | .register %g2, #scratch |
36 | .register %g2, #scratch |
37 | .register %g3, #scratch |
37 | .register %g3, #scratch |
38 | 38 | ||
39 | .section K_TEXT_START, "ax" |
39 | .section K_TEXT_START, "ax" |
40 | 40 | ||
41 | /* |
41 | /* |
42 | * Here is where the kernel is passed control |
42 | * Here is where the kernel is passed control |
43 | * from the boot loader. |
43 | * from the boot loader. |
44 | * |
44 | * |
45 | * The registers are expected to be in this state: |
45 | * The registers are expected to be in this state: |
46 | * - %o0 non-zero for the bootstrup processor, zero for application/secondary processors |
46 | * - %o0 non-zero for the bootstrap processor, zero for application/secondary processors |
47 | * - %o1 bootinfo structure address |
47 | * - %o1 bootinfo structure address |
48 | * - %o2 bootinfo structure size |
48 | * - %o2 bootinfo structure size |
49 | * |
49 | * |
50 | * Moreover, we depend on boot having established the |
50 | * Moreover, we depend on boot having established the |
51 | * following environment: |
51 | * following environment: |
52 | * - TLBs are on |
52 | * - TLBs are on |
53 | * - identity mapping for the kernel image |
53 | * - identity mapping for the kernel image |
54 | * - identity mapping for memory stack |
54 | * - identity mapping for memory stack |
55 | */ |
55 | */ |
56 | 56 | ||
57 | .global kernel_image_start |
57 | .global kernel_image_start |
58 | kernel_image_start: |
58 | kernel_image_start: |
59 | brz %o0, kernel_image_start ! block secondary processors |
- | |
60 | nop |
59 | mov %o0, %l7 |
61 | 60 | ||
62 | /* |
61 | /* |
63 | * Setup basic runtime environment. |
62 | * Setup basic runtime environment. |
64 | */ |
63 | */ |
65 | 64 | ||
66 | flushw ! flush all but the active register window |
65 | flushw ! flush all but the active register window |
67 | 66 | ||
68 | wrpr %g0, 0, %tl ! TL = 0, primary context register is used |
67 | wrpr %g0, 0, %tl ! TL = 0, primary context register is used |
69 | 68 | ||
70 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
69 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking. |
71 | 70 | ||
72 | wrpr %g0, 0, %pil ! intialize %pil |
71 | wrpr %g0, 0, %pil ! intialize %pil |
73 | 72 | ||
74 | /* |
73 | /* |
75 | * Copy the bootinfo structure passed from the boot loader |
74 | * Copy the bootinfo structure passed from the boot loader |
76 | * to the kernel bootinfo structure. |
75 | * to the kernel bootinfo structure. |
77 | */ |
76 | */ |
- | 77 | brz %l7, 0f ! skip if you are not the bootstrap CPU |
|
78 | sethi %hi(bootinfo), %o0 |
78 | sethi %hi(bootinfo), %o0 |
79 | call memcpy |
79 | call memcpy |
80 | or %o0, %lo(bootinfo), %o0 |
80 | or %o0, %lo(bootinfo), %o0 |
- | 81 | 0: |
|
81 | 82 | ||
82 | /* |
83 | /* |
83 | * Switch to kernel trap table. |
84 | * Switch to kernel trap table. |
84 | */ |
85 | */ |
85 | sethi %hi(trap_table), %g1 |
86 | sethi %hi(trap_table), %g1 |
86 | wrpr %g1, %lo(trap_table), %tba |
87 | wrpr %g1, %lo(trap_table), %tba |
87 | 88 | ||
88 | /* |
89 | /* |
89 | * Take over the DMMU by installing global locked |
90 | * Take over the DMMU by installing global locked |
90 | * TTE entry identically mapping the first 4M |
91 | * TTE entry identically mapping the first 4M |
91 | * of memory. |
92 | * of memory. |
92 | * |
93 | * |
93 | * In case of DMMU, no FLUSH instructions need to be |
94 | * In case of DMMU, no FLUSH instructions need to be |
94 | * issued. Because of that, the old DTLB contents can |
95 | * issued. Because of that, the old DTLB contents can |
95 | * be demapped pretty straightforwardly and without |
96 | * be demapped pretty straightforwardly and without |
96 | * causing any traps. |
97 | * causing any traps. |
97 | */ |
98 | */ |
98 | 99 | ||
99 | wr %g0, ASI_DMMU, %asi |
100 | wr %g0, ASI_DMMU, %asi |
100 | 101 | ||
101 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
102 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
102 | set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1 |
103 | set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1 |
103 | 104 | ||
104 | ! demap context 0 |
105 | ! demap context 0 |
105 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
106 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
106 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
107 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
107 | membar #Sync |
108 | membar #Sync |
108 | 109 | ||
109 | #define SET_TLB_TAG(r1, context) \ |
110 | #define SET_TLB_TAG(r1, context) \ |
110 | set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
111 | set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
111 | 112 | ||
112 | ! write DTLB tag |
113 | ! write DTLB tag |
113 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
114 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
114 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
115 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
115 | membar #Sync |
116 | membar #Sync |
116 | 117 | ||
117 | #define SET_TLB_DATA(r1, r2, imm) \ |
118 | #define SET_TLB_DATA(r1, r2, imm) \ |
118 | set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \ |
119 | set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \ |
119 | set PAGESIZE_4M, %r2; \ |
120 | set PAGESIZE_4M, %r2; \ |
120 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
121 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
121 | or %r1, %r2, %r1; \ |
122 | or %r1, %r2, %r1; \ |
122 | mov 1, %r2; \ |
123 | mov 1, %r2; \ |
123 | sllx %r2, TTE_V_SHIFT, %r2; \ |
124 | sllx %r2, TTE_V_SHIFT, %r2; \ |
124 | or %r1, %r2, %r1; |
125 | or %r1, %r2, %r1; |
125 | 126 | ||
126 | ! write DTLB data and install the kernel mapping |
127 | ! write DTLB data and install the kernel mapping |
127 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
128 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
128 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
129 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
129 | membar #Sync |
130 | membar #Sync |
130 | 131 | ||
131 | /* |
132 | /* |
132 | * Because we cannot use global mappings (because we want to |
133 | * Because we cannot use global mappings (because we want to |
133 | * have separate 64-bit address spaces for both the kernel |
134 | * have separate 64-bit address spaces for both the kernel |
134 | * and the userspace), we prepare the identity mapping also in |
135 | * and the userspace), we prepare the identity mapping also in |
135 | * context 1. This step is required by the |
136 | * context 1. This step is required by the |
136 | * code installing the ITLB mapping. |
137 | * code installing the ITLB mapping. |
137 | */ |
138 | */ |
138 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
139 | ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
139 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
140 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
140 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
141 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
141 | membar #Sync |
142 | membar #Sync |
142 | 143 | ||
143 | ! write DTLB data and install the kernel mapping in context 1 |
144 | ! write DTLB data and install the kernel mapping in context 1 |
144 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
145 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
145 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
146 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
146 | membar #Sync |
147 | membar #Sync |
147 | 148 | ||
148 | /* |
149 | /* |
149 | * Now is time to take over the IMMU. |
150 | * Now is time to take over the IMMU. |
150 | * Unfortunatelly, it cannot be done as easily as the DMMU, |
151 | * Unfortunatelly, it cannot be done as easily as the DMMU, |
151 | * because the IMMU is mapping the code it executes. |
152 | * because the IMMU is mapping the code it executes. |
152 | * |
153 | * |
153 | * [ Note that brave experiments with disabling the IMMU |
154 | * [ Note that brave experiments with disabling the IMMU |
154 | * and using the DMMU approach failed after a dozen |
155 | * and using the DMMU approach failed after a dozen |
155 | * of desparate days with only little success. ] |
156 | * of desparate days with only little success. ] |
156 | * |
157 | * |
157 | * The approach used here is inspired from OpenBSD. |
158 | * The approach used here is inspired from OpenBSD. |
158 | * First, the kernel creates IMMU mapping for itself |
159 | * First, the kernel creates IMMU mapping for itself |
159 | * in context 1 (MEM_CONTEXT_TEMP) and switches to |
160 | * in context 1 (MEM_CONTEXT_TEMP) and switches to |
160 | * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
161 | * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
161 | * afterwards and replaced with the kernel permanent |
162 | * afterwards and replaced with the kernel permanent |
162 | * mapping. Finally, the kernel switches back to |
163 | * mapping. Finally, the kernel switches back to |
163 | * context 0 and demaps context 1. |
164 | * context 0 and demaps context 1. |
164 | * |
165 | * |
165 | * Moreover, the IMMU requires use of the FLUSH instructions. |
166 | * Moreover, the IMMU requires use of the FLUSH instructions. |
166 | * But that is OK because we always use operands with |
167 | * But that is OK because we always use operands with |
167 | * addresses already mapped by the taken over DTLB. |
168 | * addresses already mapped by the taken over DTLB. |
168 | */ |
169 | */ |
169 | 170 | ||
170 | set kernel_image_start, %g5 |
171 | set kernel_image_start, %g5 |
171 | 172 | ||
172 | ! write ITLB tag of context 1 |
173 | ! write ITLB tag of context 1 |
173 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
174 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
174 | mov VA_DMMU_TAG_ACCESS, %g2 |
175 | mov VA_DMMU_TAG_ACCESS, %g2 |
175 | stxa %g1, [%g2] ASI_IMMU |
176 | stxa %g1, [%g2] ASI_IMMU |
176 | flush %g5 |
177 | flush %g5 |
177 | 178 | ||
178 | ! write ITLB data and install the temporary mapping in context 1 |
179 | ! write ITLB data and install the temporary mapping in context 1 |
179 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
180 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
180 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
181 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
181 | flush %g5 |
182 | flush %g5 |
182 | 183 | ||
183 | ! switch to context 1 |
184 | ! switch to context 1 |
184 | mov MEM_CONTEXT_TEMP, %g1 |
185 | mov MEM_CONTEXT_TEMP, %g1 |
185 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
186 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
186 | flush %g5 |
187 | flush %g5 |
187 | 188 | ||
188 | ! demap context 0 |
189 | ! demap context 0 |
189 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
190 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
190 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
191 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
191 | flush %g5 |
192 | flush %g5 |
192 | 193 | ||
193 | ! write ITLB tag of context 0 |
194 | ! write ITLB tag of context 0 |
194 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
195 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
195 | mov VA_DMMU_TAG_ACCESS, %g2 |
196 | mov VA_DMMU_TAG_ACCESS, %g2 |
196 | stxa %g1, [%g2] ASI_IMMU |
197 | stxa %g1, [%g2] ASI_IMMU |
197 | flush %g5 |
198 | flush %g5 |
198 | 199 | ||
199 | ! write ITLB data and install the permanent kernel mapping in context 0 |
200 | ! write ITLB data and install the permanent kernel mapping in context 0 |
200 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
201 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
201 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
202 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
202 | flush %g5 |
203 | flush %g5 |
203 | 204 | ||
204 | ! switch to context 0 |
205 | ! switch to context 0 |
205 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
206 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
206 | flush %g5 |
207 | flush %g5 |
207 | 208 | ||
208 | ! ensure nucleus mapping |
209 | ! ensure nucleus mapping |
209 | wrpr %g0, 1, %tl |
210 | wrpr %g0, 1, %tl |
210 | 211 | ||
211 | ! set context 1 in the primary context register |
212 | ! set context 1 in the primary context register |
212 | mov MEM_CONTEXT_TEMP, %g1 |
213 | mov MEM_CONTEXT_TEMP, %g1 |
213 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
214 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
214 | flush %g5 |
215 | flush %g5 |
215 | 216 | ||
216 | ! demap context 1 |
217 | ! demap context 1 |
217 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
218 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
218 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
219 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
219 | flush %g5 |
220 | flush %g5 |
220 | 221 | ||
221 | ! set context 0 in the primary context register |
222 | ! set context 0 in the primary context register |
222 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
223 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
223 | flush %g5 |
224 | flush %g5 |
224 | 225 | ||
225 | ! set TL back to 0 |
226 | ! set TL back to 0 |
226 | wrpr %g0, 0, %tl |
227 | wrpr %g0, 0, %tl |
227 | 228 | ||
- | 229 | brz %l7, 2f ! skip if you are not the bootstrap CPU |
|
- | 230 | ||
228 | call arch_pre_main |
231 | call arch_pre_main |
229 | nop |
232 | nop |
230 | 233 | ||
231 | call main_bsp |
234 | call main_bsp |
232 | nop |
235 | nop |
233 | 236 | ||
234 | /* Not reached. */ |
237 | /* Not reached. */ |
235 | 238 | ||
236 | 2: |
239 | 2: |
237 | b 2b |
240 | b 2b |
238 | nop |
241 | nop |
239 | 242 | ||
240 | 243 | ||
241 |
|
244 |
|
242 | 245 | ||
243 | 246 | ||
244 | 247 |