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#
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#
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# Copyright (C) 2005 Jakub Jermar
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# Copyright (C) 2005 Jakub Jermar
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# All rights reserved.
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# All rights reserved.
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#
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#
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# Redistribution and use in source and binary forms, with or without
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
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# - Redistributions of source code must retain the above copyright
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#   notice, this list of conditions and the following disclaimer.
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#   notice, this list of conditions and the following disclaimer.
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# - Redistributions in binary form must reproduce the above copyright
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# - Redistributions in binary form must reproduce the above copyright
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#   notice, this list of conditions and the following disclaimer in the
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#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
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#   documentation and/or other materials provided with the distribution.
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# - The name of the author may not be used to endorse or promote products
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# - The name of the author may not be used to endorse or promote products
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#   derived from this software without specific prior written permission.
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#   derived from this software without specific prior written permission.
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#
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/regdef.h>
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#include <arch/regdef.h>
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#include <arch/boot/boot.h>
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#include <arch/boot/boot.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/tte.h>
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#include <arch/mm/tte.h>
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.register %g2, #scratch
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.register %g2, #scratch
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.register %g3, #scratch
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.register %g3, #scratch
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.register %g6, #scratch
-
 
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.register %g7, #scratch
-
 
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38
 
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.section K_TEXT_START, "ax"
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.section K_TEXT_START, "ax"
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40
 
43
/*
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/*
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 * Here is where the kernel is passed control
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 * Here is where the kernel is passed control
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 * from the boot loader.
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 * from the boot loader.
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 * 
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 * 
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 * The registers are expected to be in this state:
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 * The registers are expected to be in this state:
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 * - %o0 bootinfo structure address
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 * - %o0 bootinfo structure address
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 * - %o1 bootinfo structure size
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 * - %o1 bootinfo structure size
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 *
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 *
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 * Moreover, we depend on boot having established the
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 * Moreover, we depend on boot having established the
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 * following environment:
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 * following environment:
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 * - TLBs are on
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 * - TLBs are on
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 * - identity mapping for the kernel image
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 * - identity mapping for the kernel image
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 * - identity mapping for memory stack
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 * - identity mapping for memory stack
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 */
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 */
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.global kernel_image_start
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.global kernel_image_start
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kernel_image_start:
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kernel_image_start:
60
 
58
 
61
	/*
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	/*
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	 * Setup basic runtime environment.
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	 * Setup basic runtime environment.
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	 */
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	 */
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62
 
65
	flushw				! flush all but the active register window
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	flushw				! flush all but the active register window
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	wrpr %g0, 0, %tl		! TL = 0, primary context register is used
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	wrpr %g0, 0, %tl		! TL = 0, primary context register is used
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65
 
68
	! Disable interrupts and disable 32-bit address masking.
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	! Disable interrupts and disable 32-bit address masking.
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	rdpr %pstate, %g1
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	rdpr %pstate, %g1
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	and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1
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	and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1
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	wrpr %g1, 0, %pstate
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	wrpr %g1, 0, %pstate
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70
 
73
	wrpr %r0, 0, %pil		! intialize %pil
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	wrpr %r0, 0, %pil		! intialize %pil
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72
 
75
	/*
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	/*
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	 * Copy the bootinfo structure passed from the boot loader
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	 * Copy the bootinfo structure passed from the boot loader
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	 * to the kernel bootinfo structure.
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	 * to the kernel bootinfo structure.
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	 */
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	 */
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	mov %o1, %o2
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	mov %o1, %o2
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	mov %o0, %o1
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	mov %o0, %o1
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	set bootinfo, %o0
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	set bootinfo, %o0
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	call memcpy
80
	call memcpy
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	nop
81
	nop
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82
 
85
	/*
83
	/*
86
	 * Switch to kernel trap table.
84
	 * Switch to kernel trap table.
87
	 */
85
	 */
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	set trap_table, %g1
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	set trap_table, %g1
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	wrpr %g1, 0, %tba
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	wrpr %g1, 0, %tba
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88
 
91
	/* 
89
	/* 
92
	 * Take over the DMMU by installing global locked
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	 * Take over the DMMU by installing global locked
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	 * TTE entry identically mapping the first 4M
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	 * TTE entry identically mapping the first 4M
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	 * of memory.
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	 * of memory.
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	 *
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	 *
96
	 * In case of DMMU, no FLUSH instructions need to be
94
	 * In case of DMMU, no FLUSH instructions need to be
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	 * issued. Because of that, the old DTLB contents can
95
	 * issued. Because of that, the old DTLB contents can
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	 * be demapped pretty straightforwardly and without
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	 * be demapped pretty straightforwardly and without
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	 * causing any traps.
97
	 * causing any traps.
100
	 */
98
	 */
101
 
99
 
102
	wr %g0, ASI_DMMU, %asi
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	wr %g0, ASI_DMMU, %asi
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101
 
104
#define SET_TLB_DEMAP_CMD(r1, context_id) \
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#define SET_TLB_DEMAP_CMD(r1, context_id) \
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	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
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	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
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104
	
107
	! demap context 0
105
	! demap context 0
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	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
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	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
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	stxa %g0, [%g1] ASI_DMMU_DEMAP			
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	stxa %g0, [%g1] ASI_DMMU_DEMAP			
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	membar #Sync
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	membar #Sync
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#define SET_TLB_TAG(r1, context) \
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#define SET_TLB_TAG(r1, context) \
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	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
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	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
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112
 
115
	! write DTLB tag
113
	! write DTLB tag
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
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	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
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	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
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	membar #Sync
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	membar #Sync
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117
 
120
#define SET_TLB_DATA(r1, r2, imm) \
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#define SET_TLB_DATA(r1, r2, imm) \
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	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
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	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
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	set PAGESIZE_4M, %r2; \
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	set PAGESIZE_4M, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
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	sllx %r2, TTE_SIZE_SHIFT, %r2; \
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	or %r1, %r2, %r1; \
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	or %r1, %r2, %r1; \
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	set 1, %r2; \
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	set 1, %r2; \
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	sllx %r2, TTE_V_SHIFT, %r2; \
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	sllx %r2, TTE_V_SHIFT, %r2; \
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	or %r1, %r2, %r1;
125
	or %r1, %r2, %r1;
128
	
126
	
129
	! write DTLB data and install the kernel mapping
127
	! write DTLB data and install the kernel mapping
130
	SET_TLB_DATA(g1, g2, TTE_G)
128
	SET_TLB_DATA(g1, g2, TTE_G)
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	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
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	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
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	membar #Sync
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	membar #Sync
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131
	
134
	/*
132
	/*
135
	 * Now is time to take over the IMMU.
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	 * Now is time to take over the IMMU.
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	 * Unfortunatelly, it cannot be done as easily as the DMMU,
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	 * Unfortunatelly, it cannot be done as easily as the DMMU,
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	 * because the IMMU is mapping the code it executes.
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	 * because the IMMU is mapping the code it executes.
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	 *
136
	 *
139
	 * [ Note that brave experiments with disabling the IMMU
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	 * [ Note that brave experiments with disabling the IMMU
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	 * and using the DMMU approach failed after a dozen
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	 * and using the DMMU approach failed after a dozen
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	 * of desparate days with only little success. ]
139
	 * of desparate days with only little success. ]
142
	 *
140
	 *
143
	 * The approach used here is inspired from OpenBSD.
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	 * The approach used here is inspired from OpenBSD.
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	 * First, the kernel creates IMMU mapping for itself
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	 * First, the kernel creates IMMU mapping for itself
145
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
143
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
146
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
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	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
147
	 * afterwards and replaced with the kernel permanent
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	 * afterwards and replaced with the kernel permanent
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	 * mapping. Finally, the kernel switches back to
146
	 * mapping. Finally, the kernel switches back to
149
	 * context 0 and demaps context 1.
147
	 * context 0 and demaps context 1.
150
	 *
148
	 *
151
	 * Moreover, the IMMU requires use of the FLUSH instructions.
149
	 * Moreover, the IMMU requires use of the FLUSH instructions.
152
	 * But that is OK because we always use operands with
150
	 * But that is OK because we always use operands with
153
	 * addresses already mapped by the taken over DTLB.
151
	 * addresses already mapped by the taken over DTLB.
154
	 */
152
	 */
155
	
153
	
156
	set kernel_image_start, %g7
154
	set kernel_image_start, %g5
157
	
155
	
158
	! write ITLB tag of context 1
156
	! write ITLB tag of context 1
159
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
157
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
160
	set VA_DMMU_TAG_ACCESS, %g2
158
	set VA_DMMU_TAG_ACCESS, %g2
161
	stxa %g1, [%g2] ASI_IMMU
159
	stxa %g1, [%g2] ASI_IMMU
162
	flush %g7
160
	flush %g5
163
 
161
 
164
	! write ITLB data and install the temporary mapping in context 1
162
	! write ITLB data and install the temporary mapping in context 1
165
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
163
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
166
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
164
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
167
	flush %g7
165
	flush %g5
168
	
166
	
169
	! switch to context 1
167
	! switch to context 1
170
	set MEM_CONTEXT_TEMP, %g1
168
	set MEM_CONTEXT_TEMP, %g1
171
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
169
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
172
	flush %g7
170
	flush %g5
173
	
171
	
174
	! demap context 0
172
	! demap context 0
175
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
173
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
176
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
174
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
177
	flush %g7
175
	flush %g5
178
	
176
	
179
	! write ITLB tag of context 0
177
	! write ITLB tag of context 0
180
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
178
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
181
	set VA_DMMU_TAG_ACCESS, %g2
179
	set VA_DMMU_TAG_ACCESS, %g2
182
	stxa %g1, [%g2] ASI_IMMU
180
	stxa %g1, [%g2] ASI_IMMU
183
	flush %g7
181
	flush %g5
184
 
182
 
185
	! write ITLB data and install the permanent kernel mapping in context 0
183
	! write ITLB data and install the permanent kernel mapping in context 0
186
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
184
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
187
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
185
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
188
	flush %g7
186
	flush %g5
189
 
187
 
190
	! switch to context 0
188
	! switch to context 0
191
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
189
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
192
	flush %g7
190
	flush %g5
193
 
191
 
194
	! ensure nucleus mapping
192
	! ensure nucleus mapping
195
	wrpr %g0, 1, %tl
193
	wrpr %g0, 1, %tl
196
 
194
 
197
	! set context 1 in the primary context register
195
	! set context 1 in the primary context register
198
	set MEM_CONTEXT_TEMP, %g1
196
	set MEM_CONTEXT_TEMP, %g1
199
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
197
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
200
	flush %g7
198
	flush %g5
201
 
199
 
202
	! demap context 1
200
	! demap context 1
203
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
201
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
204
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
202
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
205
	flush %g7
203
	flush %g5
206
	
204
	
207
	! set context 0 in the primary context register
205
	! set context 0 in the primary context register
208
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
206
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
209
	flush %g7
207
	flush %g5
210
	
208
	
211
	! set TL back to 0
209
	! set TL back to 0
212
	wrpr %g0, 0, %tl
210
	wrpr %g0, 0, %tl
213
	
211
	
214
	call main_bsp
212
	call main_bsp
215
	nop
213
	nop
216
 
214
 
217
	/* Not reached. */
215
	/* Not reached. */
218
 
216
 
219
2:
217
2:
220
	b 2b
218
	b 2b
221
	nop
219
	nop
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Generated by GNU Enscript 1.6.6.
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Generated by GNU Enscript 1.6.6.
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