WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/arch.h>
#include <arch/regdef.h>
#include <arch/boot/boot.h>
#include <arch/stack.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
#ifdef CONFIG_SMP
#include <arch/context_offset.h>
#endif
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
#define BSP_FLAG	1
 
/*
 * Here is where the kernel is passed control from the boot loader.
 
 * 
 * The registers are expected to be in this state:
 * - %o0 starting address of physical memory + bootstrap processor flag
 * 	bits 63...1:	physical memory starting address / 2
 *	bit 0:		non-zero on BSP processor, zero on AP processors
 * - %o1 bootinfo structure address (BSP only)
 * - %o2 bootinfo structure size (BSP only)
 *
 * Moreover, we depend on boot having established the following environment:
 
 * - TLBs are on
 * - identity mapping for the kernel image
 */
 
.global kernel_image_start
kernel_image_start:
	mov BSP_FLAG, %l0
	and %o0, %l0, %l7				! l7 <= bootstrap processor?
	andn %o0, %l0, %l6				! l6 <= start of physical memory
 
	sethi %hi(physmem_base), %l5
	stx %l6, [%l5 + %lo(physmem_base)]
 
	/*
	 * Get bits 40:13 of physmem_base.
	 */ 
	sethi %hi(mask_40_13), %l4
	sethi %hi(physmem_base_40_13), %l3
	ldx [%l4 + %lo(mask_40_13)], %l4
	and %l6, %l4, %l5				! l5 <= physmem_base[40:13]
	stx %l5, [%l3 + %lo(physmem_base_40_13)]
 
	/*
	 * Prepare kernel 8K TLB data template.
	 */
	sethi %hi(kernel_8k_tlb_data_template), %l4
	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
	or %l3, %l5, %l3
	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
	
	/*
	 * Setup basic runtime environment.
	 */
 
	wrpr %g0, NWINDOWS - 2, %cansave	! set maximum saveable windows
	wrpr %g0, 0, %canrestore		! get rid of windows we will never need again
	wrpr %g0, 0, %otherwin			! make sure the window state is consistent
	wrpr %g0, NWINDOWS - 1, %cleanwin	! prevent needless clean_window traps for kernel
 
	wrpr %g0, 0, %tl			! TL = 0, primary context register is used
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! Disable interrupts and disable 32-bit address masking.
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
	or %r1, %l5, %r1; \
	mov PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	mov 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
 
	/*
	 * Because we cannot use global mappings (because we want to
	 * have separate 64-bit address spaces for both the kernel
	 * and the userspace), we prepare the identity mapping also in
	 * context 1. This step is required by the
	 * code installing the ITLB mapping.
	 */
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
	! write DTLB data and install the kernel mapping in context 1
	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! enter nucleus - using context 0
	wrpr %g0, 1, %tl
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! leave nucleus - using primary context, i.e. context 0
	wrpr %g0, 0, %tl
 
	brz %l7, 1f				! skip if you are not the bootstrap CPU
	nop
 
	/*
	 * So far, we have not touched the stack.
	 * It is a good idea to set the kernel stack to a known state now.
	 */
	sethi %hi(temporary_boot_stack), %sp
	or %sp, %lo(temporary_boot_stack), %sp
	sub %sp, STACK_BIAS, %sp
 
	sethi %hi(bootinfo), %o0
	call memcpy				! copy bootinfo
	or %o0, %lo(bootinfo), %o0
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
0:
	ba 0b
	nop
 
 
	/*
	 * Read MID from the processor.
	 */
1:
	ldxa [%g0] ASI_UPA_CONFIG, %g1
	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
	and %g1, UPA_CONFIG_MID_MASK, %g1
 
#ifdef CONFIG_SMP
	/*
	 * Active loop for APs until the BSP picks them up.
	 * A processor cannot leave the loop until the
	 * global variable 'waking_up_mid' equals its
	 * MID.
	 */
	set waking_up_mid, %g2
2:
	ldx [%g2], %g3
	cmp %g3, %g1
	bne 2b
	nop
 
	/*
	 * Configure stack for the AP.
	 * The AP is expected to use the stack saved
	 * in the ctx global variable.
	 */
	set ctx, %g1
	add %g1, OFFSET_SP, %g1
	ldx [%g1], %o6
 
	call main_ap
	nop
 
	/* Not reached. */
#endif
	
0:
	ba 0b
	nop
 
 
.section K_DATA_START, "aw", @progbits
 
/*
 * Create small stack to be used by the bootstrap processor.
 * It is going to be used only for a very limited period of
 * time, but we switch to it anyway, just to be sure we are
 * properly initialized.
 *
 * What is important is that this piece of memory is covered
 * by the 4M DTLB locked entry and therefore there will be
 * no surprises like deadly combinations of spill trap and
 * and TLB miss on the stack address.
 */
 
#define INITIAL_STACK_SIZE	1024
 
.align STACK_ALIGNMENT
	.space INITIAL_STACK_SIZE
.align STACK_ALIGNMENT
temporary_boot_stack:
	.space STACK_WINDOW_SAVE_AREA_SIZE
 
 
.data
 
.align 8
.global physmem_base		! copy of the physical memory base address
physmem_base:
	.quad 0
 
.global physmem_base_40_13
physmem_base_40_13:		! physmem_base & mask_40_13
	.quad 0
 
.global mask_40_13
mask_40_13:			! constant with bits 40:13 set
	.quad (((1 << 41) - 1) & ~((1 << 13) - 1))
 
/*
 * This variable is used by the fast_data_MMU_miss trap handler.
 * It is initialized to reflect the starting address of physical
 * memory.
 */
.global kernel_8k_tlb_data_template
kernel_8k_tlb_data_template:
	.quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W)
 
 

Rev 1975	Rev 1978
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/arch.h>	29	#include <arch/arch.h>
30	#include <arch/regdef.h>	30	#include <arch/regdef.h>
31	#include <arch/boot/boot.h>	31	#include <arch/boot/boot.h>
32	#include <arch/stack.h>	32	#include <arch/stack.h>
33		33
34	#include <arch/mm/mmu.h>	34	#include <arch/mm/mmu.h>
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <arch/mm/tte.h>	36	#include <arch/mm/tte.h>
37		37
38	#ifdef CONFIG_SMP	38	#ifdef CONFIG_SMP
39	#include <arch/context_offset.h>	39	#include <arch/context_offset.h>
40	#endif	40	#endif
41		41
42	.register %g2, #scratch	42	.register %g2, #scratch
43	.register %g3, #scratch	43	.register %g3, #scratch
44		44
45	.section K_TEXT_START, "ax"	45	.section K_TEXT_START, "ax"
46		46
-		47	#define BSP_FLAG 1
-		48
47	/*	49	/*
48	* Here is where the kernel is passed control	50	* Here is where the kernel is passed control from the boot loader.
49	* from the boot loader.	-
50	*	51	*
51	* The registers are expected to be in this state:	52	* The registers are expected to be in this state:
-		53	* - %o0 starting address of physical memory + bootstrap processor flag
-		54	* bits 63...1: physical memory starting address / 2
52	* - %o0 non-zero for the bootstrap processor, zero for application/secondary processors	55	* bit 0: non-zero on BSP processor, zero on AP processors
53	* - %o1 bootinfo structure address	56	* - %o1 bootinfo structure address (BSP only)
54	* - %o2 bootinfo structure size	57	* - %o2 bootinfo structure size (BSP only)
55	*	58	*
56	* Moreover, we depend on boot having established the	59	* Moreover, we depend on boot having established the following environment:
57	* following environment:	-
58	* - TLBs are on	60	* - TLBs are on
59	* - identity mapping for the kernel image	61	* - identity mapping for the kernel image
60	*/	62	*/
61		63
62	.global kernel_image_start	64	.global kernel_image_start
63	kernel_image_start:	65	kernel_image_start:
64	mov %o0, %l7	66	mov BSP_FLAG, %l0
-		67	and %o0, %l0, %l7 ! l7 <= bootstrap processor?
-		68	andn %o0, %l0, %l6 ! l6 <= start of physical memory
-		69
-		70	sethi %hi(physmem_base), %l5
-		71	stx %l6, [%l5 + %lo(physmem_base)]
-		72
-		73	/*
-		74	* Get bits 40:13 of physmem_base.
-		75	*/
-		76	sethi %hi(mask_40_13), %l4
-		77	sethi %hi(physmem_base_40_13), %l3
-		78	ldx [%l4 + %lo(mask_40_13)], %l4
-		79	and %l6, %l4, %l5 ! l5 <= physmem_base[40:13]
-		80	stx %l5, [%l3 + %lo(physmem_base_40_13)]
65		81
66	/*	82	/*
-		83	* Prepare kernel 8K TLB data template.
-		84	*/
-		85	sethi %hi(kernel_8k_tlb_data_template), %l4
-		86	ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
-		87	or %l3, %l5, %l3
-		88	stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
-		89
-		90	/*
67	* Setup basic runtime environment.	91	* Setup basic runtime environment.
68	*/	92	*/
69		93
70	wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows	94	wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows
71	wrpr %g0, 0, %canrestore ! get rid of windows we will never need again	95	wrpr %g0, 0, %canrestore ! get rid of windows we will never need again
72	wrpr %g0, 0, %otherwin ! make sure the window state is consistent	96	wrpr %g0, 0, %otherwin ! make sure the window state is consistent
73	wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel	97	wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window traps for kernel
74		98
75	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	99	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
76		100
77	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.	101	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
78		102
79	wrpr %g0, 0, %pil ! intialize %pil	103	wrpr %g0, 0, %pil ! intialize %pil
80		104
81	/*	105	/*
82	* Switch to kernel trap table.	106	* Switch to kernel trap table.
83	*/	107	*/
84	sethi %hi(trap_table), %g1	108	sethi %hi(trap_table), %g1
85	wrpr %g1, %lo(trap_table), %tba	109	wrpr %g1, %lo(trap_table), %tba
86		110
87	/*	111	/*
88	* Take over the DMMU by installing global locked	112	* Take over the DMMU by installing global locked
89	* TTE entry identically mapping the first 4M	113	* TTE entry identically mapping the first 4M
90	* of memory.	114	* of memory.
91	*	115	*
92	* In case of DMMU, no FLUSH instructions need to be	116	* In case of DMMU, no FLUSH instructions need to be
93	* issued. Because of that, the old DTLB contents can	117	* issued. Because of that, the old DTLB contents can
94	* be demapped pretty straightforwardly and without	118	* be demapped pretty straightforwardly and without
95	* causing any traps.	119	* causing any traps.
96	*/	120	*/
97		121
98	wr %g0, ASI_DMMU, %asi	122	wr %g0, ASI_DMMU, %asi
99		123
100	#define SET_TLB_DEMAP_CMD(r1, context_id) \	124	#define SET_TLB_DEMAP_CMD(r1, context_id) \
101	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	125	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
102		126
103	! demap context 0	127	! demap context 0
104	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	128	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
105	stxa %g0, [%g1] ASI_DMMU_DEMAP	129	stxa %g0, [%g1] ASI_DMMU_DEMAP
106	membar #Sync	130	membar #Sync
107		131
108	#define SET_TLB_TAG(r1, context) \	132	#define SET_TLB_TAG(r1, context) \
109	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	133	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
110		134
111	! write DTLB tag	135	! write DTLB tag
112	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	136	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
113	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	137	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
114	membar #Sync	138	membar #Sync
115		139
116	#define SET_TLB_DATA(r1, r2, imm) \	140	#define SET_TLB_DATA(r1, r2, imm) \
117	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \	141	set TTE_CV \| TTE_CP \| TTE_P \| LMA \| imm, %r1; \
-		142	or %r1, %l5, %r1; \
118	set PAGESIZE_4M, %r2; \	143	mov PAGESIZE_4M, %r2; \
119	sllx %r2, TTE_SIZE_SHIFT, %r2; \	144	sllx %r2, TTE_SIZE_SHIFT, %r2; \
120	or %r1, %r2, %r1; \	145	or %r1, %r2, %r1; \
121	mov 1, %r2; \	146	mov 1, %r2; \
122	sllx %r2, TTE_V_SHIFT, %r2; \	147	sllx %r2, TTE_V_SHIFT, %r2; \
123	or %r1, %r2, %r1;	148	or %r1, %r2, %r1;
124		149
125	! write DTLB data and install the kernel mapping	150	! write DTLB data and install the kernel mapping
126	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping	151	SET_TLB_DATA(g1, g2, TTE_L \| TTE_W) ! use non-global mapping
127	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	152	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
128	membar #Sync	153	membar #Sync
129		154
130	/*	155	/*
131	* Because we cannot use global mappings (because we want to	156	* Because we cannot use global mappings (because we want to
132	* have separate 64-bit address spaces for both the kernel	157	* have separate 64-bit address spaces for both the kernel
133	* and the userspace), we prepare the identity mapping also in	158	* and the userspace), we prepare the identity mapping also in
134	* context 1. This step is required by the	159	* context 1. This step is required by the
135	* code installing the ITLB mapping.	160	* code installing the ITLB mapping.
136	*/	161	*/
137	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)	162	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
138	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	163	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
139	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	164	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
140	membar #Sync	165	membar #Sync
141		166
142	! write DTLB data and install the kernel mapping in context 1	167	! write DTLB data and install the kernel mapping in context 1
143	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping	168	SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping
144	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	169	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
145	membar #Sync	170	membar #Sync
146		171
147	/*	172	/*
148	* Now is time to take over the IMMU.	173	* Now is time to take over the IMMU.
149	* Unfortunatelly, it cannot be done as easily as the DMMU,	174	* Unfortunatelly, it cannot be done as easily as the DMMU,
150	* because the IMMU is mapping the code it executes.	175	* because the IMMU is mapping the code it executes.
151	*	176	*
152	* [ Note that brave experiments with disabling the IMMU	177	* [ Note that brave experiments with disabling the IMMU
153	* and using the DMMU approach failed after a dozen	178	* and using the DMMU approach failed after a dozen
154	* of desparate days with only little success. ]	179	* of desparate days with only little success. ]
155	*	180	*
156	* The approach used here is inspired from OpenBSD.	181	* The approach used here is inspired from OpenBSD.
157	* First, the kernel creates IMMU mapping for itself	182	* First, the kernel creates IMMU mapping for itself
158	* in context 1 (MEM_CONTEXT_TEMP) and switches to	183	* in context 1 (MEM_CONTEXT_TEMP) and switches to
159	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	184	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
160	* afterwards and replaced with the kernel permanent	185	* afterwards and replaced with the kernel permanent
161	* mapping. Finally, the kernel switches back to	186	* mapping. Finally, the kernel switches back to
162	* context 0 and demaps context 1.	187	* context 0 and demaps context 1.
163	*	188	*
164	* Moreover, the IMMU requires use of the FLUSH instructions.	189	* Moreover, the IMMU requires use of the FLUSH instructions.
165	* But that is OK because we always use operands with	190	* But that is OK because we always use operands with
166	* addresses already mapped by the taken over DTLB.	191	* addresses already mapped by the taken over DTLB.
167	*/	192	*/
168		193
169	set kernel_image_start, %g5	194	set kernel_image_start, %g5
170		195
171	! write ITLB tag of context 1	196	! write ITLB tag of context 1
172	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	197	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
173	mov VA_DMMU_TAG_ACCESS, %g2	198	mov VA_DMMU_TAG_ACCESS, %g2
174	stxa %g1, [%g2] ASI_IMMU	199	stxa %g1, [%g2] ASI_IMMU
175	flush %g5	200	flush %g5
176		201
177	! write ITLB data and install the temporary mapping in context 1	202	! write ITLB data and install the temporary mapping in context 1
178	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	203	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
179	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	204	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
180	flush %g5	205	flush %g5
181		206
182	! switch to context 1	207	! switch to context 1
183	mov MEM_CONTEXT_TEMP, %g1	208	mov MEM_CONTEXT_TEMP, %g1
184	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	209	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
185	flush %g5	210	flush %g5
186		211
187	! demap context 0	212	! demap context 0
188	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	213	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
189	stxa %g0, [%g1] ASI_IMMU_DEMAP	214	stxa %g0, [%g1] ASI_IMMU_DEMAP
190	flush %g5	215	flush %g5
191		216
192	! write ITLB tag of context 0	217	! write ITLB tag of context 0
193	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	218	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
194	mov VA_DMMU_TAG_ACCESS, %g2	219	mov VA_DMMU_TAG_ACCESS, %g2
195	stxa %g1, [%g2] ASI_IMMU	220	stxa %g1, [%g2] ASI_IMMU
196	flush %g5	221	flush %g5
197		222
198	! write ITLB data and install the permanent kernel mapping in context 0	223	! write ITLB data and install the permanent kernel mapping in context 0
199	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping	224	SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping
200	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	225	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
201	flush %g5	226	flush %g5
202		227
203	! enter nucleus - using context 0	228	! enter nucleus - using context 0
204	wrpr %g0, 1, %tl	229	wrpr %g0, 1, %tl
205		230
206	! demap context 1	231	! demap context 1
207	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	232	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
208	stxa %g0, [%g1] ASI_IMMU_DEMAP	233	stxa %g0, [%g1] ASI_IMMU_DEMAP
209	flush %g5	234	flush %g5
210		235
211	! set context 0 in the primary context register	236	! set context 0 in the primary context register
212	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	237	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
213	flush %g5	238	flush %g5
214		239
215	! leave nucleus - using primary context, i.e. context 0	240	! leave nucleus - using primary context, i.e. context 0
216	wrpr %g0, 0, %tl	241	wrpr %g0, 0, %tl
217		242
218	brz %l7, 1f ! skip if you are not the bootstrap CPU	243	brz %l7, 1f ! skip if you are not the bootstrap CPU
219	nop	244	nop
220		245
221	/*	246	/*
222	* So far, we have not touched the stack.	247	* So far, we have not touched the stack.
223	* It is a good idea to set the kernel stack to a known state now.	248	* It is a good idea to set the kernel stack to a known state now.
224	*/	249	*/
225	sethi %hi(temporary_boot_stack), %sp	250	sethi %hi(temporary_boot_stack), %sp
226	or %sp, %lo(temporary_boot_stack), %sp	251	or %sp, %lo(temporary_boot_stack), %sp
227	sub %sp, STACK_BIAS, %sp	252	sub %sp, STACK_BIAS, %sp
228		253
229	sethi %hi(bootinfo), %o0	254	sethi %hi(bootinfo), %o0
230	call memcpy ! copy bootinfo	255	call memcpy ! copy bootinfo
231	or %o0, %lo(bootinfo), %o0	256	or %o0, %lo(bootinfo), %o0
232		257
233	call arch_pre_main	258	call arch_pre_main
234	nop	259	nop
235		260
236	call main_bsp	261	call main_bsp
237	nop	262	nop
238		263
239	/* Not reached. */	264	/* Not reached. */
240		265
241	0:	266	0:
242	ba 0b	267	ba 0b
243	nop	268	nop
244		269
245		270
246	/*	271	/*
247	* Read MID from the processor.	272	* Read MID from the processor.
248	*/	273	*/
249	1:	274	1:
250	ldxa [%g0] ASI_UPA_CONFIG, %g1	275	ldxa [%g0] ASI_UPA_CONFIG, %g1
251	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1	276	srlx %g1, UPA_CONFIG_MID_SHIFT, %g1
252	and %g1, UPA_CONFIG_MID_MASK, %g1	277	and %g1, UPA_CONFIG_MID_MASK, %g1
253		278
254	#ifdef CONFIG_SMP	279	#ifdef CONFIG_SMP
255	/*	280	/*
256	* Active loop for APs until the BSP picks them up.	281	* Active loop for APs until the BSP picks them up.
257	* A processor cannot leave the loop until the	282	* A processor cannot leave the loop until the
258	* global variable 'waking_up_mid' equals its	283	* global variable 'waking_up_mid' equals its
259	* MID.	284	* MID.
260	*/	285	*/
261	set waking_up_mid, %g2	286	set waking_up_mid, %g2
262	2:	287	2:
263	ldx [%g2], %g3	288	ldx [%g2], %g3
264	cmp %g3, %g1	289	cmp %g3, %g1
265	bne 2b	290	bne 2b
266	nop	291	nop
267		292
268	/*	293	/*
269	* Configure stack for the AP.	294	* Configure stack for the AP.
270	* The AP is expected to use the stack saved	295	* The AP is expected to use the stack saved
271	* in the ctx global variable.	296	* in the ctx global variable.
272	*/	297	*/
273	set ctx, %g1	298	set ctx, %g1
274	add %g1, OFFSET_SP, %g1	299	add %g1, OFFSET_SP, %g1
275	ldx [%g1], %o6	300	ldx [%g1], %o6
276		301
277	call main_ap	302	call main_ap
278	nop	303	nop
279		304
280	/* Not reached. */	305	/* Not reached. */
281	#endif	306	#endif
282		307
283	0:	308	0:
284	ba 0b	309	ba 0b
285	nop	310	nop
286		311
287		312
288	.section K_DATA_START, "aw", @progbits	313	.section K_DATA_START, "aw", @progbits
289		314
290	/*	315	/*
291	* Create small stack to be used by the bootstrap processor.	316	* Create small stack to be used by the bootstrap processor.
292	* It is going to be used only for a very limited period of	317	* It is going to be used only for a very limited period of
293	* time, but we switch to it anyway, just to be sure we are	318	* time, but we switch to it anyway, just to be sure we are
294	* properly initialized.	319	* properly initialized.
295	*	320	*
296	* What is important is that this piece of memory is covered	321	* What is important is that this piece of memory is covered
297	* by the 4M DTLB locked entry and therefore there will be	322	* by the 4M DTLB locked entry and therefore there will be
298	* no surprises like deadly combinations of spill trap and	323	* no surprises like deadly combinations of spill trap and
299	* and TLB miss on the stack address.	324	* and TLB miss on the stack address.
300	*/	325	*/
301		326
302	#define INITIAL_STACK_SIZE 1024	327	#define INITIAL_STACK_SIZE 1024
303		328
304	.align STACK_ALIGNMENT	329	.align STACK_ALIGNMENT
305	.space INITIAL_STACK_SIZE	330	.space INITIAL_STACK_SIZE
306	.align STACK_ALIGNMENT	331	.align STACK_ALIGNMENT
307	temporary_boot_stack:	332	temporary_boot_stack:
308	.space STACK_WINDOW_SAVE_AREA_SIZE	333	.space STACK_WINDOW_SAVE_AREA_SIZE
-		334
-		335
-		336	.data
-		337
-		338	.align 8
-		339	.global physmem_base ! copy of the physical memory base address
-		340	physmem_base:
-		341	.quad 0
-		342
-		343	.global physmem_base_40_13
-		344	physmem_base_40_13: ! physmem_base & mask_40_13
-		345	.quad 0
-		346
-		347	.global mask_40_13
-		348	mask_40_13: ! constant with bits 40:13 set
-		349	.quad (((1 << 41) - 1) & ~((1 << 13) - 1))
-		350
-		351	/*
-		352	* This variable is used by the fast_data_MMU_miss trap handler.
-		353	* It is initialized to reflect the starting address of physical
-		354	* memory.
-		355	*/
-		356	.global kernel_8k_tlb_data_template
-		357	kernel_8k_tlb_data_template:
-		358	.quad ((1 << TTE_V_SHIFT) \| TTE_CV \| TTE_CP \| TTE_P \| TTE_W)
-		359
309		360

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(root)/trunk/kernel/arch/sparc64/src/start.S – Rev 1975 → 1978