WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/start.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/regdef.h>
#include <arch/boot/boot.h>
 
#include <arch/mm/mmu.h>
#include <arch/mm/tlb.h>
#include <arch/mm/tte.h>
 
.register %g2, #scratch
.register %g3, #scratch
 
.section K_TEXT_START, "ax"
 
/*
 * Here is where the kernel is passed control
 * from the boot loader.
 * 
 * The registers are expected to be in this state:
 * - %o0 bootinfo structure address
 * - %o1 bootinfo structure size
 *
 * Moreover, we depend on boot having established the
 * following environment:
 * - TLBs are on
 * - identity mapping for the kernel image
 * - identity mapping for memory stack
 */
 
.global kernel_image_start
kernel_image_start:
 
	/*
	 * Setup basic runtime environment.
	 */
 
	flushw					! flush all but the active register window
 
 
	wrpr %g0, 0, %tl			! TL = 0, primary context register is used
 
 
 
 
	wrpr %g0, PSTATE_PRIV_BIT, %pstate	! Disable interrupts and disable 32-bit address masking.
 
	wrpr %g0, 0, %pil			! intialize %pil
 
	/*
	 * Copy the bootinfo structure passed from the boot loader
	 * to the kernel bootinfo structure.
	 */
	mov %o1, %o2
	mov %o0, %o1
	sethi %hi(bootinfo), %o0
	call memcpy
	or %o0, %lo(bootinfo), %o0
 
	/*
	 * Switch to kernel trap table.
	 */
	sethi %hi(trap_table), %g1
	wrpr %g1, %lo(trap_table), %tba
 
	/* 
	 * Take over the DMMU by installing global locked
	 * TTE entry identically mapping the first 4M
	 * of memory.
	 *
	 * In case of DMMU, no FLUSH instructions need to be
	 * issued. Because of that, the old DTLB contents can
	 * be demapped pretty straightforwardly and without
	 * causing any traps.
	 */
 
	wr %g0, ASI_DMMU, %asi
 
#define SET_TLB_DEMAP_CMD(r1, context_id) \
	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) | (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_DMMU_DEMAP			
	membar #Sync
 
#define SET_TLB_TAG(r1, context) \
	set VMA | (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
 
	! write DTLB tag
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
#define SET_TLB_DATA(r1, r2, imm) \
	set TTE_L | TTE_CP | TTE_P | TTE_W | LMA | imm, %r1; \
	set PAGESIZE_4M, %r2; \
	sllx %r2, TTE_SIZE_SHIFT, %r2; \
	or %r1, %r2, %r1; \
	mov 1, %r2; \
	sllx %r2, TTE_V_SHIFT, %r2; \
	or %r1, %r2, %r1;
	
	! write DTLB data and install the kernel mapping
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
 
	/*
	 * Because we cannot use global mappings (because we want to
	 * have separate 64-bit address spaces for both the kernel
	 * and the userspace), we prepare the identity mapping also in
	 * context 1. This step is required by the
	 * code installing the ITLB mapping.
	 */
	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
	membar #Sync
 
	! write DTLB data and install the kernel mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
	membar #Sync
	
	/*
	 * Now is time to take over the IMMU.
	 * Unfortunatelly, it cannot be done as easily as the DMMU,
	 * because the IMMU is mapping the code it executes.
	 *
	 * [ Note that brave experiments with disabling the IMMU
	 * and using the DMMU approach failed after a dozen
	 * of desparate days with only little success. ]
	 *
	 * The approach used here is inspired from OpenBSD.
	 * First, the kernel creates IMMU mapping for itself
	 * in context 1 (MEM_CONTEXT_TEMP) and switches to
	 * it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
	 * afterwards and replaced with the kernel permanent
	 * mapping. Finally, the kernel switches back to
	 * context 0 and demaps context 1.
	 *
	 * Moreover, the IMMU requires use of the FLUSH instructions.
	 * But that is OK because we always use operands with
	 * addresses already mapped by the taken over DTLB.
	 */
	
	set kernel_image_start, %g5
	
	! write ITLB tag of context 1
	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the temporary mapping in context 1
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
	
	! switch to context 1
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! demap context 0
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! write ITLB tag of context 0
	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
	mov VA_DMMU_TAG_ACCESS, %g2
	stxa %g1, [%g2] ASI_IMMU
	flush %g5
 
	! write ITLB data and install the permanent kernel mapping in context 0
	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
	flush %g5
 
	! switch to context 0
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! ensure nucleus mapping
	wrpr %g0, 1, %tl
 
	! set context 1 in the primary context register
	mov MEM_CONTEXT_TEMP, %g1
	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
 
	! demap context 1
	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
	stxa %g0, [%g1] ASI_IMMU_DEMAP			
	flush %g5
	
	! set context 0 in the primary context register
	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi	! ASI_DMMU is correct here !!!
	flush %g5
	
	! set TL back to 0
	wrpr %g0, 0, %tl
 
	call arch_pre_main
	nop
	
	call main_bsp
	nop
 
	/* Not reached. */
 
2:
	b 2b
	nop
 

Rev 1880	Rev 1881
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	#include <arch/regdef.h>	29	#include <arch/regdef.h>
30	#include <arch/boot/boot.h>	30	#include <arch/boot/boot.h>
31		31
32	#include <arch/mm/mmu.h>	32	#include <arch/mm/mmu.h>
33	#include <arch/mm/tlb.h>	33	#include <arch/mm/tlb.h>
34	#include <arch/mm/tte.h>	34	#include <arch/mm/tte.h>
35		35
36	.register %g2, #scratch	36	.register %g2, #scratch
37	.register %g3, #scratch	37	.register %g3, #scratch
38		38
39	.section K_TEXT_START, "ax"	39	.section K_TEXT_START, "ax"
40		40
41	/*	41	/*
42	* Here is where the kernel is passed control	42	* Here is where the kernel is passed control
43	* from the boot loader.	43	* from the boot loader.
44	*	44	*
45	* The registers are expected to be in this state:	45	* The registers are expected to be in this state:
46	* - %o0 bootinfo structure address	46	* - %o0 bootinfo structure address
47	* - %o1 bootinfo structure size	47	* - %o1 bootinfo structure size
48	*	48	*
49	* Moreover, we depend on boot having established the	49	* Moreover, we depend on boot having established the
50	* following environment:	50	* following environment:
51	* - TLBs are on	51	* - TLBs are on
52	* - identity mapping for the kernel image	52	* - identity mapping for the kernel image
53	* - identity mapping for memory stack	53	* - identity mapping for memory stack
54	*/	54	*/
55		55
56	.global kernel_image_start	56	.global kernel_image_start
57	kernel_image_start:	57	kernel_image_start:
58		58
59	/*	59	/*
60	* Setup basic runtime environment.	60	* Setup basic runtime environment.
61	*/	61	*/
62		62
63	flushw ! flush all but the active register window	63	flushw ! flush all but the active register window
64	wrpr %g0, 0, %tl ! TL = 0, primary context register is used	-
65		64
66	! Disable interrupts and disable 32-bit address masking.	65	wrpr %g0, 0, %tl ! TL = 0, primary context register is used
67	rdpr %pstate, %g1	-
68	and %g1, ~(PSTATE_AM_BIT\|PSTATE_IE_BIT), %g1	-
69	wrpr %g1, 0, %pstate	-
70		66
-		67	wrpr %g0, PSTATE_PRIV_BIT, %pstate ! Disable interrupts and disable 32-bit address masking.
-		68
71	wrpr %g0, 0, %pil ! intialize %pil	69	wrpr %g0, 0, %pil ! intialize %pil
72		70
73	/*	71	/*
74	* Copy the bootinfo structure passed from the boot loader	72	* Copy the bootinfo structure passed from the boot loader
75	* to the kernel bootinfo structure.	73	* to the kernel bootinfo structure.
76	*/	74	*/
77	mov %o1, %o2	75	mov %o1, %o2
78	mov %o0, %o1	76	mov %o0, %o1
79	sethi %hi(bootinfo), %o0	77	sethi %hi(bootinfo), %o0
80	call memcpy	78	call memcpy
81	or %o0, %lo(bootinfo), %o0	79	or %o0, %lo(bootinfo), %o0
82		80
83	/*	81	/*
84	* Switch to kernel trap table.	82	* Switch to kernel trap table.
85	*/	83	*/
86	sethi %hi(trap_table), %g1	84	sethi %hi(trap_table), %g1
87	wrpr %g1, %lo(trap_table), %tba	85	wrpr %g1, %lo(trap_table), %tba
88		86
89	/*	87	/*
90	* Take over the DMMU by installing global locked	88	* Take over the DMMU by installing global locked
91	* TTE entry identically mapping the first 4M	89	* TTE entry identically mapping the first 4M
92	* of memory.	90	* of memory.
93	*	91	*
94	* In case of DMMU, no FLUSH instructions need to be	92	* In case of DMMU, no FLUSH instructions need to be
95	* issued. Because of that, the old DTLB contents can	93	* issued. Because of that, the old DTLB contents can
96	* be demapped pretty straightforwardly and without	94	* be demapped pretty straightforwardly and without
97	* causing any traps.	95	* causing any traps.
98	*/	96	*/
99		97
100	wr %g0, ASI_DMMU, %asi	98	wr %g0, ASI_DMMU, %asi
101		99
102	#define SET_TLB_DEMAP_CMD(r1, context_id) \	100	#define SET_TLB_DEMAP_CMD(r1, context_id) \
103	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1	101	set (TLB_DEMAP_CONTEXT<<TLB_DEMAP_TYPE_SHIFT) \| (context_id<<TLB_DEMAP_CONTEXT_SHIFT), %r1
104		102
105	! demap context 0	103	! demap context 0
106	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	104	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
107	stxa %g0, [%g1] ASI_DMMU_DEMAP	105	stxa %g0, [%g1] ASI_DMMU_DEMAP
108	membar #Sync	106	membar #Sync
109		107
110	#define SET_TLB_TAG(r1, context) \	108	#define SET_TLB_TAG(r1, context) \
111	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1	109	set VMA \| (context<<TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
112		110
113	! write DTLB tag	111	! write DTLB tag
114	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	112	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
115	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	113	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
116	membar #Sync	114	membar #Sync
117		115
118	#define SET_TLB_DATA(r1, r2, imm) \	116	#define SET_TLB_DATA(r1, r2, imm) \
119	set TTE_L \| TTE_CP \| TTE_P \| TTE_W \| LMA \| imm, %r1; \	117	set TTE_L \| TTE_CP \| TTE_P \| TTE_W \| LMA \| imm, %r1; \
120	set PAGESIZE_4M, %r2; \	118	set PAGESIZE_4M, %r2; \
121	sllx %r2, TTE_SIZE_SHIFT, %r2; \	119	sllx %r2, TTE_SIZE_SHIFT, %r2; \
122	or %r1, %r2, %r1; \	120	or %r1, %r2, %r1; \
123	mov 1, %r2; \	121	mov 1, %r2; \
124	sllx %r2, TTE_V_SHIFT, %r2; \	122	sllx %r2, TTE_V_SHIFT, %r2; \
125	or %r1, %r2, %r1;	123	or %r1, %r2, %r1;
126		124
127	! write DTLB data and install the kernel mapping	125	! write DTLB data and install the kernel mapping
128	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	126	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
129	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	127	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
130	membar #Sync	128	membar #Sync
131		129
132	/*	130	/*
133	* Because we cannot use global mappings (because we want to	131	* Because we cannot use global mappings (because we want to
134	* have separate 64-bit address spaces for both the kernel	132	* have separate 64-bit address spaces for both the kernel
135	* and the userspace), we prepare the identity mapping also in	133	* and the userspace), we prepare the identity mapping also in
136	* context 1. This step is required by the	134	* context 1. This step is required by the
137	* code installing the ITLB mapping.	135	* code installing the ITLB mapping.
138	*/	136	*/
139	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)	137	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
140	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	138	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
141	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi	139	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
142	membar #Sync	140	membar #Sync
143		141
144	! write DTLB data and install the kernel mapping in context 1	142	! write DTLB data and install the kernel mapping in context 1
145	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	143	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
146	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG	144	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
147	membar #Sync	145	membar #Sync
148		146
149	/*	147	/*
150	* Now is time to take over the IMMU.	148	* Now is time to take over the IMMU.
151	* Unfortunatelly, it cannot be done as easily as the DMMU,	149	* Unfortunatelly, it cannot be done as easily as the DMMU,
152	* because the IMMU is mapping the code it executes.	150	* because the IMMU is mapping the code it executes.
153	*	151	*
154	* [ Note that brave experiments with disabling the IMMU	152	* [ Note that brave experiments with disabling the IMMU
155	* and using the DMMU approach failed after a dozen	153	* and using the DMMU approach failed after a dozen
156	* of desparate days with only little success. ]	154	* of desparate days with only little success. ]
157	*	155	*
158	* The approach used here is inspired from OpenBSD.	156	* The approach used here is inspired from OpenBSD.
159	* First, the kernel creates IMMU mapping for itself	157	* First, the kernel creates IMMU mapping for itself
160	* in context 1 (MEM_CONTEXT_TEMP) and switches to	158	* in context 1 (MEM_CONTEXT_TEMP) and switches to
161	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped	159	* it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
162	* afterwards and replaced with the kernel permanent	160	* afterwards and replaced with the kernel permanent
163	* mapping. Finally, the kernel switches back to	161	* mapping. Finally, the kernel switches back to
164	* context 0 and demaps context 1.	162	* context 0 and demaps context 1.
165	*	163	*
166	* Moreover, the IMMU requires use of the FLUSH instructions.	164	* Moreover, the IMMU requires use of the FLUSH instructions.
167	* But that is OK because we always use operands with	165	* But that is OK because we always use operands with
168	* addresses already mapped by the taken over DTLB.	166	* addresses already mapped by the taken over DTLB.
169	*/	167	*/
170		168
171	set kernel_image_start, %g5	169	set kernel_image_start, %g5
172		170
173	! write ITLB tag of context 1	171	! write ITLB tag of context 1
174	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)	172	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
175	mov VA_DMMU_TAG_ACCESS, %g2	173	mov VA_DMMU_TAG_ACCESS, %g2
176	stxa %g1, [%g2] ASI_IMMU	174	stxa %g1, [%g2] ASI_IMMU
177	flush %g5	175	flush %g5
178		176
179	! write ITLB data and install the temporary mapping in context 1	177	! write ITLB data and install the temporary mapping in context 1
180	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	178	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
181	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	179	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
182	flush %g5	180	flush %g5
183		181
184	! switch to context 1	182	! switch to context 1
185	mov MEM_CONTEXT_TEMP, %g1	183	mov MEM_CONTEXT_TEMP, %g1
186	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	184	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
187	flush %g5	185	flush %g5
188		186
189	! demap context 0	187	! demap context 0
190	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)	188	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
191	stxa %g0, [%g1] ASI_IMMU_DEMAP	189	stxa %g0, [%g1] ASI_IMMU_DEMAP
192	flush %g5	190	flush %g5
193		191
194	! write ITLB tag of context 0	192	! write ITLB tag of context 0
195	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)	193	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
196	mov VA_DMMU_TAG_ACCESS, %g2	194	mov VA_DMMU_TAG_ACCESS, %g2
197	stxa %g1, [%g2] ASI_IMMU	195	stxa %g1, [%g2] ASI_IMMU
198	flush %g5	196	flush %g5
199		197
200	! write ITLB data and install the permanent kernel mapping in context 0	198	! write ITLB data and install the permanent kernel mapping in context 0
201	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping	199	SET_TLB_DATA(g1, g2, 0) ! use non-global mapping
202	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG	200	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
203	flush %g5	201	flush %g5
204		202
205	! switch to context 0	203	! switch to context 0
206	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	204	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
207	flush %g5	205	flush %g5
208		206
209	! ensure nucleus mapping	207	! ensure nucleus mapping
210	wrpr %g0, 1, %tl	208	wrpr %g0, 1, %tl
211		209
212	! set context 1 in the primary context register	210	! set context 1 in the primary context register
213	mov MEM_CONTEXT_TEMP, %g1	211	mov MEM_CONTEXT_TEMP, %g1
214	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	212	stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
215	flush %g5	213	flush %g5
216		214
217	! demap context 1	215	! demap context 1
218	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)	216	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
219	stxa %g0, [%g1] ASI_IMMU_DEMAP	217	stxa %g0, [%g1] ASI_IMMU_DEMAP
220	flush %g5	218	flush %g5
221		219
222	! set context 0 in the primary context register	220	! set context 0 in the primary context register
223	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!	221	stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
224	flush %g5	222	flush %g5
225		223
226	! set TL back to 0	224	! set TL back to 0
227	wrpr %g0, 0, %tl	225	wrpr %g0, 0, %tl
228		226
229	call arch_pre_main	227	call arch_pre_main
230	nop	228	nop
231		229
232	call main_bsp	230	call main_bsp
233	nop	231	nop
234		232
235	/* Not reached. */	233	/* Not reached. */
236		234
237	2:	235	2:
238	b 2b	236	b 2b
239	nop	237	nop
240		238

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(root)/trunk/kernel/arch/sparc64/src/start.S @ 1954 – Rev 1880 → 1881